similar to: [LLVMdev] Separate loop condition and loop body

On Mon, Jun 30, 2014 at 02:40:43AM -0700, Quentin Colombet wrote: > Hi Arsen, > > > > On Jun 19, 2014, at 10:43 PM, Arsen Hakobyan <artinetstudio at gmail.com> wrote: > > > > Hi all, > > > > I want to generate an assembly instruction for my target using target > > description representation of the instruction. The problem is that I want to

Hi all, I want to generate an assembly instruction for my target using target description representation of the instruction. The problem is that I want to add direct register to be chose as an output register for my target. Does it possible to do with an instruction definition in TARGETInstrInfo.td file? May be someone could help with an example? Currently I have seen that we can pass the name

>>> To me it looks like any basic block from the loop body with a >>> successor not in the loop body is a BB "building the condition" (an >>> "exit" block). >> Consider break statements (CFG attached): while (j < 10 && j > 5 && j % 2 == 0) { j++; if (j == 9) break; } In this example, block

Hi Arsen, On Oct 9, 2013, at 4:53 AM, Arsen Hakobyan <artinetstudio at gmail.com> wrote: > Hi all, > > I have the following test case: > #define FLT_EPSILON 1.19209290E-7 > > int err = -1; > int main() > { > float a = 8.1; > if (((a - 8.1) >= FLT_EPSILON) || ((a - 8.1) <= -FLT_EPSILON)) { //I am > using FLT_EPSILON to check whether (a != 2.0).

Hi all, I have the following test case: #define FLT_EPSILON 1.19209290E-7 int err = -1; int main() { float a = 8.1; if (((a - 8.1) >= FLT_EPSILON) || ((a - 8.1) <= -FLT_EPSILON)) { //I am using FLT_EPSILON to check whether (a != 2.0). err = 1; } else { err = 0; } return 0; } with -O3 optimization level clang generates already incorrect LLVM IR: ; Function Attrs:

Dear Tom, What is the advantage to use the “pseudo instruction” approach VS “custom lowering/DAGtoDAGSelection” VS “ Library function”? Best Kevin On Aug 14, 2014, at 9:27 AM, Tom Stellard <tom at stellard.net> wrote: > On Thu, Aug 14, 2014 at 12:05:33AM -0700, Arsen Hakobyan wrote: >> Hi all, >> >> I would like to be sure that Tablegen still does not support

Hi all, I would like to be sure that Tablegen still does not support completely separate multiple instruction generation, and the only way is to write costume code (may be in TargetISelDAGToDAG class) to get the needed result. Dear Tom, do you found other solution (using Tablegen tool) for this? Thanks, Arsen -- View this message in context:

The sign information for binary operators is available in the llvm IR by the 'nsw' (no signed wrap) flag. Seems there is no use of this flag in the code generation phase. The sign information is no more available in the selection DAG. So how can I generate different instructions for binary operators with signed/unsigned operands in the assembler (e.g. mul/mulu)? -- View this message in

Hello, I have a need to change the parameter type of llvm.lifetime.start/end intrinsic functions to get other defined type, but i do not want to replace the current definition of the intrinsic function with the new definition. Is there a way, to do such things for a specific target? If the only way to do this is to create a separate file for my target and write there a target specific

Dear all. I have a problem with the following situation: I want to handle an intrinsic function in a specific way. The prototype of my function is: "/int my_intrinsic_name()/" So I want to generate a move instruction which should use two register type operands: "/mov R1, R2/" For this purpose I assume that the instruction definition in the TargetInstrInfo.td file

+ Adrian + David Hi Arsen, This sounds like a bug to me. Have you tried reproducing it on trunk? For instance, I see that the relation between DICompileUnit and DISubprogram was changed in the meantime (https://reviews.llvm.org/D19034 <https://reviews.llvm.org/D19034>). If this no longer occurs on master you could bisect the compiler to find the commit(s) that fix this and consider

Thanks Paul, Hi Adrian and David I would really appreciate any comments, thoughts assumptions. If additional information is needed please let me know. Regards, Arsen On Sat, Jan 13, 2018 at 2:54 AM, Robinson, Paul <paul.robinson at sony.com> wrote: > Hi Arsen, we are beyond what I understand about how metadata operates. > Maybe Adrian or David knows. > > --paulr > >

Hi, Is it possible to get the list of BasicBlocks building the condition of a loop and the list of BasicBlocks that form the body? My first approach was to iterate over the list of all Basicblocks of a loop and separate the header as the condition and the remaining as the body of the loop. However, this is not correct for instance in the case of a while loop in the form: while( A & B) do {

Hi Arsen, we are beyond what I understand about how metadata operates. Maybe Adrian or David knows. --paulr From: Arsen Hakobyan [mailto:hakobyan.ars at gmail.com] Sent: Friday, January 12, 2018 12:16 PM To: Robinson, Paul Cc: llvm-dev at lists.llvm.org; David Blaikie Subject: Re: [llvm-dev] StripDeadDebugInfo for static inline functions. Just one update: the function causing the segmentation

Hi Arsen, I wrote a pass that computes a control dependence graph as described in Ferrante et al's "The Program Dependence Graph and Its Use in Optimization." It is available at https://github.com/thinkmoore/llvm-analysis. Cheers, Scott On Fri, Apr 12, 2013 at 5:04 PM, John Criswell <criswell at illinois.edu>wrote: > On 4/12/13 3:19 PM, Arsen wrote: > >> Thank

Just one update: the function causing the segmentation fault is the following: 359 void DwarfDebug::constructAbstractSubprogramScopeDIE(LexicalScope *Scope) { 360 assert(Scope && Scope->getScopeNode()); 361 assert(Scope->isAbstractScope()); 362 assert(!Scope->getInlinedAt()); 363 364 const MDNode *SP = Scope->getScopeNode(); 365 366

On Mon, May 10, 2010 at 12:32:06PM -0700, Trevor Harmon wrote: > On May 10, 2010, at 11:35 AM, Benoit Boissinot wrote: > > >To me it looks like any basic block from the loop body with a > >successor not in the loop body is a BB "building the condition" (an > >"exit" block). > > I assume you mean "any basic block from the loop header".

On 4/12/13 2:37 PM, Arsen wrote: > Hello All, > > I am interested in Control Dependence Graph building using the CFG and > Dominance Frontier provided by corresponding passes. Just wandering whether > LLVM provides some kind of pass or builder which will generate the Control > Dependence Graph? I think the PostDominanceFrontier analysis was removed from LLVM, but the

Hi Paul, Thanks for your response. Let me actually post more details visualizing my case. Assuming that can help. so the IR before the opt tool is running is: ; Function Attrs: nounwind define i16 @main() #0 !dbg !13 { entry: %retval = alloca i16, align 1 ... } ; Function Attrs: inlinehint nounwind define internal void @delay(i16 %d) #4 !dbg !69 { entry: %d.addr = alloca i16,

Hello All, I am interested in Control Dependence Graph building using the CFG and Dominance Frontier provided by corresponding passes. Just wandering whether LLVM provides some kind of pass or builder which will generate the Control Dependence Graph? Thanks, Arsen -- View this message in context: http://llvm.1065342.n5.nabble.com/Control-Dependence-Graph-builder-tp56687.html Sent from the