similar to: [LLVMdev] Dynamic optimization infrastructure

Hi Bill, With the latest llvm version I'm getting the following error: opt -instnamer < core-device.c.bc > core-device.o.bc Attribute 'nobuiltin' only applies to functions! void (%struct.fw_csr_iterator*, i32*)* @fw_csr_iterator_init Broken module found, compilation aborted! 0 opt 0x0000000001914bf1 llvm::sys::PrintStackTrace(_IO_FILE*) + 38 1 opt

Dear all, I would like to share a paper I co-authored with Prof. Alper Sen. This paper describes an algorithm to generate testbenches from SystemC models represented with LLVM IR. It was accepted and presented at International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS), 2012. A link to the paper is accessible from acm or Alper's website:

Does anyone know if LLVM will soon have a dynamic optimization infrastructure, namely support to generate trampolines back to the JIT/execution manager that get run when a piece of code's frequency exceeds a threshold? I see that there already is a relinkAndRecompileFunction in the JIT, which will be useful. Rather than roll my own mechanisms and have to worry about jumping back to code that

Hi Marcelo, That should be fixed now at r184239. Sorry about the failure! -bw On Jun 17, 2013, at 6:16 AM, Marcelo Sousa <marceloabsousa at gmail.com> wrote: > Hello, > > I'm getting an error when running opt with what seems to be a valid bytecode file compiled from one the Linux Kernel files. > The error is: > opt: /home/scratch/llvm/lib/IR/Attributes.cpp:119:

Very interesting, thanks for the forward! If you're interested in having a link posted on llvm.org, please email the llvmdev mailing list. -Chris On Jan 30, 2013, at 9:42 AM, Marcelo Sousa <marceloabsousa at gmail.com> wrote: > Dear all, > > I would like to share a paper I co-authored with Prof. Alper Sen. This > paper describes an algorithm to generate testbenches from

Dear all, I'm happy to share a recent publication on a bounded model checker for concurrent programs represented in LLVM IR that integrates the verification framework that I'm developing: Marcelo Sousa, and Alper Sen, LLVMVF: A Generic Approach for Verification of Multicore Software. Journal of Electronic Testing: Theory and Applications, September 2013. (

On 4/3/13 8:21 AM, Marcelo Sousa wrote: > I am interested in type-based verification of LLVM IR in the areas of > certified compilation and software Can you explain what you mean by type-based verification? Do you mean that you want to use a set of typing rules to perform verification, or do you mean something else? > verification. It seems to me that the LLVM IR type system is

Hello, I'm getting an error when running opt with what seems to be a valid bytecode file compiled from one the Linux Kernel files. The error is: opt: /home/scratch/llvm/lib/IR/Attributes.cpp:119: llvm::StringRef llvm::Attribute::getKindAsString() const: Assertion `isStringAttribute() && "Invalid attribute type to get the kind as a string!"' failed. I send you in attach

I am interested in type-based verification of LLVM IR in the areas of certified compilation and software verification. It seems to me that the LLVM IR type system is rather informal in the sense that there is no paper with a proper formalization of the type rules, and for example, a proof of soundness for well-formedness of the code. I would like to know if you are aware of any work in this

Hello, According to the notes in [1] there was a plan to raise inline assembly blocks to the level of LLVM intrinsics or 'actual' LLVM IR. Is anyone aware of progress in this area? I'm aware that a complete solution in general is unlikely but a partial solution (that handles a subset of instructions directly mappable to the LLVM IR AST) could be very relevant. [1]

Apologies if you receive multiple copies of this call. ******************************************************************************** CALL FOR PAPERS 5th Workshop on Statistical and Machine learning approaches to ARchitecture and compilaTion

Hello, In the following code snippet: %tmp49 = call i64 asm "movq %gs:${1:P},$0", "=r,im,,~{fpsr},~{flags}"(i64* @kernel_stack) #6, !dbg !6625, !srcloc !5841 I would expect for the inline asm call to receive two arguments because of the ${1:P} corresponding to a %P1 that will append the $1 to %%gs:. Can someone explain why there is only one argument in this call? Moreover,

Hi, The MISS 2011 workshop below is highly related to this mailing list, since VMs are some of the best-known examples of systems software. Dealing with modularity in a VM is known to be critical, yet tough, so insights, advances or experiences from the trenches are extremely welcome at our workshop. Consider participating! Thanks in advance, the MISS 2011 committee

* Published in IEEE Xplore * Google Scholar H5-Index = 22 ------------------------------ ---- Doctoral Symposium of CISTI'2023 ------------------------------ ------------ CISTI'2023 - 18th Iberian Conference on Information Systems and Technologies 20 - 23 of June 2023, University of Aveiro, Aveiro, Portugal http://cisti.eu/

Hello, Is there a way to generate LLVM IR without constant expressions by promoting constant expressions to registers? e.g.: %tmp1 = tail call i8* @foo(i8* bitcast (i32* @x to i8*), i8* %tmp, i64 4) #1 would be converted to: %tmp1 = bitcast i32* @x to i8* %tmp2 = tail call i8* @foo(i8* %tmp1, i8* %tmp, i64 4) #1 I find quite inconvenient and redundant to maintain constant expressions when

Call for Papers --------------------------------------------------------------------------------------- IEEE Transaction on Cloud Computing Special Issue on Many-Task Computing in the Cloud http://datasys.cs.iit.edu/events/TCC-MTC15/ ======================================================================================= The Special Issue on Many-Task Computing (MTC) in the Cloud will provide the

Call for Papers --------------------------------------------------------------------------------------- IEEE Transaction on Cloud Computing Special Issue on Many-Task Computing in the Cloud http://datasys.cs.iit.edu/events/TCC-MTC15/ ======================================================================================= The Special Issue on Many-Task Computing (MTC) in the Cloud will provide the

Call for Papers --------------------------------------------------------------------------------------- IEEE Transaction on Cloud Computing Special Issue on Many-Task Computing in the Cloud http://datasys.cs.iit.edu/events/TCC-MTC15/ ======================================================================================= The Special Issue on Many-Task Computing (MTC) in the Cloud will provide the

Call for Papers --------------------------------------------------------------------------------------- IEEE Transaction on Cloud Computing Special Issue on Many-Task Computing in the Cloud http://datasys.cs.iit.edu/events/TCC-MTC15/ ======================================================================================= The Special Issue on Many-Task Computing (MTC) in the Cloud will provide the

Call for Papers -------------------------------------------------------------- ------------------------- The 5th Workshop on Many-Task Computing on Grids and Supercomputers (MTAGS) 2012 http://datasys.cs.iit.edu/events/MTAGS12/ -------------------------------------------------------------- ------------------------- November 12th, 2012 Salt Lake City, Utah, USA Co-located with with