similar to: [LLVMdev] Problem with LEA_ADDri

On Dec 3, 2007, at 12:53 PM, Vladimir Prus wrote: > > Suppose I have a target that does not have register+constant > addressing mode. Then, I have DAG like: > > (store ..., (frameindex)) > > Targets like SPARC have the following patterns to catch this: > > def ADDRri : ComplexPattern<i32, 2, > "SelectADDRri", [frameindex], []>; > def STri :

Suppose I have a target that does not have register+constant addressing mode. Then, I have DAG like: (store ..., (frameindex)) Targets like SPARC have the following patterns to catch this: def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>; def STri : F3_2<3, 0b000100, (outs), (ins MEMri:$addr, IntRegs:$src),

Evan Cheng wrote: > > On Dec 3, 2007, at 12:53 PM, Vladimir Prus wrote: > >> >> Suppose I have a target that does not have register+constant >> addressing mode. Then, I have DAG like: >> >> (store ..., (frameindex)) >> >> Targets like SPARC have the following patterns to catch this: >> >> def ADDRri : ComplexPattern<i32, 2,

I'm a bit confused as to how some of the values in a Sparc store instruction actually come to be set. The Sparc backend defines a store as: def STri : F3_2<3, 0b000100, (outs), (ins MEMri:$addr, IntRegs:$src), "st $src, [$addr]", [(store IntRegs:$src, ADDRri:$addr)]>; F3_2 and it's superclasses are defined as follows:

On Oct 19, 2007, at 8:15 AM, Boris Boesler wrote: > Hi! > > I'm writing a new back-end for a new architecture. First, I'll do > some "tests" with an existing back-end (I chose the Sparc back-end). > My architecture has special address-registers and I want to add such > new address-registers to my Sparc back-end. > > 1) I defined a new register call

Hi! >> I'm writing a new back-end for a new architecture. First, I'll do >> some "tests" with an existing back-end (I chose the Sparc back-end). >> My architecture has special address-registers and I want to add such >> new address-registers to my Sparc back-end. >> .... >> The GlobalAddress for variable c is replaced by an ADD(HI(c), LO

Hi, I'm implementing __builtin_setjmp and __builtin_longjmp for Sparc 32 bit processors (64 bit later, time allowing). I'm basing the code on the PowerPC version, which itself is based on the X86 version. This code is very nearly working, and I've had it working for -O0 optimisation (with a slightly different version to that below), so I know it's close. However, the PowerPC

On Feb 13, 2007, at 11:27 AM, Evan Cheng wrote: >> >> Thanks Evan, >> >> I had tried something like this, but ran into some problems. >> >> llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1478: failed assertion >> `MVT::isVector(VT) && "Cannot promote this load!"' >> >> and >> >>

Hi! I'm writing a new back-end for a new architecture. First, I'll do some "tests" with an existing back-end (I chose the Sparc back-end). My architecture has special address-registers and I want to add such new address-registers to my Sparc back-end. 1) I defined a new register call AddrRegs 2) I registered the class AddrRegs (addRegisterClass(MVT::iPTR, .. )) 3) I

On Sun, 1 Oct 2006, Roman Levenstein wrote: > I'm trying to implement a new backend for an embedded CISC processor. > Therefore I thought that it makes sense to take X86 target as a basis, > to save some time. Ok. Note that the X86 backend is one of the most complex though, because it supports several subtargets and ABIs, which makes it more complex than some other targets. >

Hi, I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some related commits later on, and the assertion I get on the latest trunk (r164162) differs from

Hi Chris, Thanks a lot for your answer! Chris Lattner wrote: >> 1. Why does X86 instruction set description provide different >> descriptions for the same instructions, which differ only in the size >> of operands? >> E.g. >> >> def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src), >> "mov{b} {$src, $dst|$dst, $src}",

Sure I will split it and put it in two patches. Give me few hours. I need to test those patches. Sirish On 4/19/2012 8:40 AM, Tom Stellard wrote: > On Wed, Apr 18, 2012 at 11:18:05PM -0500, Sirish Pande wrote: >> Hi, >> >> Here's a patch for Hexagon Packetizer for review. This patch does >> not yield any warnings. >> > Would it be possible to split this

I want to generate the instruction like addi 40, r3 ! i.e. r3 = r3 + 40 The format i wrote is def ADDI : F1<opcode, (outs IntRegs:$dst), (ins IntRegs:$dst, i32imm:$imm) "addi $imm, $dst", [(set $IntRegs:$dst, (add $IntRegs:$dst, i32imm:$c))] but it is not compiling. what should be the format. vikram -- View this message

hi Tim,guys, it was regarding splitting 16-bit ADDC to two 8-bit ADDC+ADDE. the 8-bit ADDE instruction is defined as: let Constraints="$dst=$op0",mayStore=1, hasSideEffects=0,neverHasSideEffects=1 in def ADDErm: myInstr <0x0, (outs Intregs:$dst) (ins Intregs:$op0,MEMi:$op1), "", [set IntRegs:$dest (adde IntRegs:$op0, (load ADDRi:$op1))] > very unlucky, this

Hello > Finally, I don't know how to describe following instructions in > MCoreInstrInfo.td, because of its variable ins/outs. Or what other files > should I use to finish this description? Do you need the isel support for them? If yes, then you should custom isel them. iirc ARM and SystemZ backends have similar instructions, while only the first one supports full isel for them. In

Hi Vikram, The error message would be helpful, but the most likely problem is the duplication of $dst. It should probably be: def ADDI : F1<opcode, (outs IntRegs:$dst), (ins IntRegs:$src, i32imm:$imm) "addi $imm, $dst", [(set $IntRegs:$dst, (add $IntRegs:$src, i32imm:$c))]> { let Constraints = "$src = $dst"; } i.e. separate

> > Thanks Evan, > > I had tried something like this, but ran into some problems. > > llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1478: failed assertion > `MVT::isVector(VT) && "Cannot promote this load!"' > > and > > llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1766: failed assertion > `MVT::isVector(VT) && "Unknown legal

Hi, all: Now I'm working on writing a backend for Moto MCore, but I don't know how to describe some instructions. First, I've already written MCoreRegisterInfo.td like these: class MCoreReg<bits<4> num, string name> : Register<name> { let Namespace = "MCore"; field bits<4> Num = num; } def R0 : MCoreReg< 0, "R0">,

On Feb 12, 2007, at 12:58 PM, Evan Cheng wrote: > > On Feb 12, 2007, at 1:41 AM, Christopher Lamb wrote: > >> >> selector refused to select certain ops (specifically stores) for some >> instructions when the operand type wasn't the first type for the >> register class. After some digging around I seem to have solved the >> problem by creating bitconvert