similar to: [LLVMdev] [llvm] r181753 - This is the first of three patches which creates stubs used for

Okay to push this change? On 07/23/2013 05:17 PM, reed kotler wrote: > Hi Daniel, > > In this case we are not using lnt under Qemu user mode for benchmarking; > just as a way to run test-suite to test whether the code is correct. > > Qemu user mode emulates target instructions, but when it gets a Unix > Kernel trap, it uses the host to emulate those. > > For example,

I have run "make check", the "test-suite" on x86 and all internal mips flavors with this patch and no problems arose. On 11/04/2012 11:07 AM, Reed Kotler wrote: > The main idea is to distinguish between emitting normal labels and debug > labels. This is the nomenclature chosen by the gcc people working on > this same problem. > > I have just added one

So the switching between mips16 and mips32 on a per function basis seems to basically be working except that asm printer has some kind of issue here. I'm debugging that now. I get this: lc: /home/rkotler/workspace/llvmpb6/include/llvm/MC/MCStreamer.h:224: void llvm::MCStreamer::SwitchSection(const llvm::MCSection*): Assertion `Section && "Cannot switch to a null

This seems to work okay. I register both the Mips16 and non Mips16 passes of the instruction selector and then those return false if they are not supposed to be running. Make-check at least passes in this case. So in principle turn on the dual mode now and debug whatever misc is left. For this I insert another pass before the mips16 and non mips16 passes. On 03/27/2013 10:19 AM, Reed Kotler

No. forward() is working correctly. All virtual register references must be resolved before calling it. -Jim On Feb 5, 2013, at 4:05 PM, Reed Kotler <rkotler at mips.com> wrote: > So what I realized is that you can't use the simple scavenger trick where you create the virtual register and use the more advanced features. > > This is because you can't call forward() in any

I think that Bill Wendlings new attribute implementation would allow me to do this but it is not ready yet. Maybe it's okay to just add them to the list of function attributes as I suggested. But in the end, someone has to approve the checkin. On 01/11/2013 07:35 AM, Reed Kotler wrote: > Yes, you could have mips16 and fastcc. > > Mips16 just means that processor mode to execute

I thought of a simpler way to do this which is no more of a hack than the way labels are noramally output. Create an EmitDebugLabel and then in MCAsminfo, add another variable for the suffix for debug labels which can by default be just ":". Then for Mips I can change it to "=." On 11/03/2012 01:40 PM, Reed Kotler wrote: > I'm working on a patch for this problem

What I am thinking of now is to just register the MIPS116 and MIPS32 DAGToDAGISel passes and then within run on machine function, I can just return if the current mode indicates that mips16 is needed for example, so the run on machine function for Mips32 would return immediately. On 03/27/2013 10:05 AM, Reed Kotler wrote: > I guess another way to do this is to just register both passes for

I guess another way to do this is to just register both passes for mips16 and mips32 and have them return immediately if it is not their turn to run. On 03/27/2013 08:58 AM, Reed Kotler wrote: > I'm implementing this ability to switch between mips16 and mips32 on a > per function basis. > > One issue that I've run into is regarding the DAGToDAGIsel pass. > > We have a

In this case, you can specialize a few pass manager objects, each for a specific sub target type. E.g. PassManager pm0 = .. ; // for mips32; PassManager pm1 = .. ; // for mips16; ... if(function needs to run on mips32) pm0.run(); else if(function needs to run on mips16) pm1.run(); ... Of course, you have to figure out the suitable sets of functions for each sub target. Hope it helps.

Reed, It's not clear to me that you need to do anything special here. If you define your MIPS16 register class as not containing SP, then any MIPS16 instructions that get selected and want to read from SP should get a COPY inserted from SP to a MIPS16 vreg. The coalescer should, ideally, get rid of extraneous copies for you. --Owen On Sep 20, 2012, at 10:48 PM, Reed Kotler <rkotler at

For example: /home/rkotler/llvm/install/bin/llc -mcpu=mips16 hf16_2.ll -march=mipsel -relocation-model=pic -o hf16_2.s -O3 -mips16-hard-float -soft-float On 01/04/2013 07:45 PM, Eli Friedman wrote: > On Fri, Jan 4, 2013 at 6:28 PM, reed kotler <rkotler at mips.com> wrote: >> On 01/04/2013 06:08 PM, Eli Friedman wrote: >>> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler

I'm working on a patch for this problem for mips16; unfortunately it's a target independent patch. I'm not sure the best nomenclature for this. In the gcc mips16 patch they call "xxx=." a debug label. The other terminology they use is byte pointer vs ISA-encoded address (ISA-encoded meaning this one bit in the case of mips16 ISA). I'm planning to add a virtual method

On Sep 20, 2012, at 11:44 PM, Reed Kotler <rkotler at mips.com> wrote: > Actually, SP is already not in the mips 16 register class but there is some C++ code that is common to mips32, mips64 and mips16 that is wanting to use SP. It's kind of awkward but does work except in this case of load/store haflword and byte to stack objects. > ARM has a similar problem. The InstrInfo

Reed, On May 14, 2012, at 3:45 PM, reed kotler <rkotler at mips.com> wrote: > On 05/14/2012 02:42 PM, Jakob Stoklund Olesen wrote: >> On May 14, 2012, at 2:28 PM, reed kotler wrote: >> >>> I'm not using getMinimalPhysRegClass. Some target independent code is using it. >> Probably PEI. >> >>> It makes trouble for us and I would like to

What happens here is that the code that is doing the "softening", generates a libcall On closer inspection, llvm is doing half of this correctly. The signature for the soft float function for extending a float to double is of the form: i64 xxx_extendsfdf2(float); But it should be i64 xxx_extendsfdf2(i32) This particular paradigm is duplicated many times in the the float type

So what I realized is that you can't use the simple scavenger trick where you create the virtual register and use the more advanced features. This is because you can't call forward() in any form if there are virtual registers being used by any of the instructions in the basic block. This will cause forward to fail. Maybe this is a bug in forward() On 02/05/2013 02:51 PM, Reed Kotler

On Mon, Jan 7, 2013 at 4:16 PM, reed kotler <rkotler at mips.com> wrote: > On 01/04/2013 07:45 PM, Eli Friedman wrote: >> >> On Fri, Jan 4, 2013 at 6:28 PM, reed kotler <rkotler at mips.com> wrote: >>> >>> On 01/04/2013 06:08 PM, Eli Friedman wrote: >>>> >>>> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com>

This came about in trying to implement some stubs used by gcc mips16 for allowing floating point interoperability with mips32. You get the following looking code from gcc -mips16: # Stub function for foovf (float) .section .mips16.fn.foovf,"ax", at progbits .align 2 .set nomips16 .set nomicromips .ent __fn_stub_foovf .type __fn_stub_foovf, @function __fn_stub_foovf: la

I have two sets of features I want to add to the mips16 port. 1) A module pass that scans the IR and makes a decision as to whether to compile the given function as mips16 or mips32. Now I can specify this by adding attributes. Mips16 is just used for space optimization so the presumption is that I'm only worrying about space optimization for this pass. At a first approximation, this