Displaying 20 results from an estimated 8000 matches similar to: "[LLVMdev] Predicated Vector Operations"
2013 May 09
0
[LLVMdev] Predicated Vector Operations
On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote:
> Jeff Bush <jeffbush001 at gmail.com> writes:
>
>> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...>
>> %ty = select %mask, %y, <0.0, 0.0, 0.0 ...>
>> %sum = fadd %tx, %ty
>> %newvalue = select %mask, %sum, %oldvalue
>>
>> I believe the generated instructions depend on whether
2013 May 09
2
[LLVMdev] Predicated Vector Operations
On May 9, 2013, at 3:05 PM, Jeff Bush <jeffbush001 at gmail.com> wrote:
> On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote:
>> Jeff Bush <jeffbush001 at gmail.com> writes:
>>
>>> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...>
>>> %ty = select %mask, %y, <0.0, 0.0, 0.0 ...>
>>> %sum = fadd %tx, %ty
>>> %newvalue
2013 May 08
0
[LLVMdev] Predicated Vector Operations
Jeff Bush <jeffbush001 at gmail.com> writes:
> I'm trying to understand how predicated/masked instructions can be
> generated in llvm, specifically an instruction where a set bit in the
> mask will write the new result into the corresponding vector lane in
> the destination and a clear bit will cause the lane in the destination
> to remain what it was before the
2013 May 10
4
[LLVMdev] Predicated Vector Operations
Jeff Bush <jeffbush001 at gmail.com> writes:
> Ah, I think I get it now. This was mentioned earlier in the thread,
> but it didn't click at the time. It sounds like I can do instruction
> selection with a pattern like (omitting selection of the sources):
>
> let Constraints = "$dst = $oldvalue" in {
> def MASKEDARITH : MyInstruction<
>
2013 May 10
0
[LLVMdev] Predicated Vector Operations
Ah, I think I get it now. This was mentioned earlier in the thread,
but it didn't click at the time. It sounds like I can do instruction
selection with a pattern like (omitting selection of the sources):
let Constraints = "$dst = $oldvalue" in {
def MASKEDARITH : MyInstruction<
(outs VectorReg:$dst),
(ins MaskReg:$mask, VectorReg:$src1, VectorReg:$src2,
2013 May 10
0
[LLVMdev] Predicated Vector Operations
On May 10, 2013, at 11:53 AM, dag at cray.com wrote:
> Jeff Bush <jeffbush001 at gmail.com> writes:
>
>> Ah, I think I get it now. This was mentioned earlier in the thread,
>> but it didn't click at the time. It sounds like I can do instruction
>> selection with a pattern like (omitting selection of the sources):
>>
>> let Constraints = "$dst
2013 May 11
0
[LLVMdev] Predicated Vector Operations
On Fri, May 10, 2013 at 9:53 AM, <dag at cray.com> wrote:
> Jeff Bush <jeffbush001 at gmail.com> writes:
>
>> Ah, I think I get it now. This was mentioned earlier in the thread,
>> but it didn't click at the time. It sounds like I can do instruction
>> selection with a pattern like (omitting selection of the sources):
>>
>> let Constraints =
2020 Jun 25
2
How to implement load/store for vector predicate register
Hi, there
I am writing an backend, and I met a problem.
We don't have load/store instructions for vector predicate registers(vpr for short).
The hardware has 64 vector registers(vr for short) and 8 vector predicate registers. And there is no move instructions between vr and vpr.
vr supports many operations, and vpr supports vpror, vprxor, vprand and vprinv operations.
A vr has 512 bits, and
2020 Jun 26
2
How to implement load/store for vector predicate register
Hi,
I am planning to expanding the pseudo instructions in XXXTargetLowering::EmitInstrWithCustomInserter(), and use temporary virtual registers as operands.
If I use virtual registers, do I need to mark them as "early clobber"?
I saw that sometimes they marked virtual register as "early clobber" in EmitInstrWithCustomInserter() in MIPS backend.
What is the effect of marking a
2015 Apr 30
2
búsqueda y sustitución masiva
Hola a tod en s, explico lo que estoy intentando hacer...
Tengo un listado de url comprimidas de twitter, entre las cuales hay muchas
repetidas, por lo que el número de registros llega a más de 15K.
Por otro lado tengo otra lista de esas url únicas con su equivalente ya
descomprimido llegando a un registro de 900.
El problema que tengo es que estoy intentando hacer un loop para hacer la
2012 Feb 03
2
[LLVMdev] How to properly use copyValue?
Since there are no constructors for Value, how do you properly insert a new
Value?
If I create a pointer Value *newValue and then call AA.copyValue(oldValue,
newValue), this does not work, since newValue is not allocated.
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2012 Aug 16
3
[LLVMdev] error: instruction requires: thumb2
Hi Everybody,
I recently did a cross-compiling using clang (built with host=x86, target=arm) with the following command:
> clang -march=armv7-a -mfloat-abi=soft -ccc-host-triple arm-none-linux-gnueabi -integrated-as main.c -o main.o -c
and get error message:
-------------------------------------------------------
main.c:9:9: error: instruction requires: thumb2
"ldrex
2012 Feb 04
0
[LLVMdev] How to properly use copyValue?
Ryan Taylor wrote:
> Since there are no constructors for Value, how do you properly insert a
> new Value?
Value is a pure base. If you want to construct a new Value, then you
want to construct a global variable or instruction or argument or
something in particular.
> If I create a pointer Value *newValue and then call
> AA.copyValue(oldValue, newValue), this does not work, since
2012 Feb 05
1
[LLVMdev] How to properly use copyValue?
Nick,
First, thanks for responding. Secondly, I just want to create an exact
copy of an already exisitng Value, this should be pretty simple to do but
I'm unclear on how to do this?
For example, PHINode::getIncomingValue (unsigned) returns a "Value" and I
want to make a copy of that Value. Is there some other way to do this other
than copyValue() that I'm missing?
On Sat,
2012 Aug 16
0
[LLVMdev] error: instruction requires: thumb2
On Thu, Aug 16, 2012 at 12:55 PM, Lei Zhao <leizhao833 at gmail.com> wrote:
> Hi Everybody,
>
> I recently did a cross-compiling using clang (built with host=x86, target=arm) with the following command:
>
> > clang -march=armv7-a -mfloat-abi=soft -ccc-host-triple arm-none-linux-gnueabi -integrated-as main.c -o main.o -c
>
> and get error message:
>
>
2012 Aug 16
2
[LLVMdev] error: instruction requires: thumb2
It works. But a follow-up question: why do I have to compile it to thumb mode in order to pass the compilation? Is there a way to make it compile to regular arm mode? Thanks.
- Lei
On Aug 16, 2012, at 4:00 PM, Eli Friedman wrote:
> On Thu, Aug 16, 2012 at 12:55 PM, Lei Zhao <leizhao833 at gmail.com> wrote:
>> Hi Everybody,
>>
>> I recently did a cross-compiling
2007 Oct 03
4
form_remote_tag :onsubmit not working.
Hi,
Has anyone successfully implemented the :onsubmit option for
form_remote_tag. It doesn''t seem to work for me. Is there any specific
version of rails which is required for the same.
Here''s my piece of code.
<script>
function set_tojid(){
alert(''onsubmit'');
}
</script>
<%= form_remote_tag :update => '''', :url => {
2020 Nov 06
4
Loop-vectorizer prototype for the EPI Project based on the RISC-V Vector Extension (Scalable vectors)
On 11/6/20 8:49 AM, Roger Ferrer Ibáñez wrote:
Hi Sjoerd,
Trying to remember how everything fits together here, but could get.active.lane.mask not create the %mask of the VP intrinsics? Or in other words, in the vectoriser, who's producing the %mask and %evl that is consumed by the VP intrinsics?
I'm not sure what would be the best way here. I think about the Loop Vectorizer. I imagine
2011 Dec 02
18
[LLVMdev] RFC: Machine Instruction Bundle
Machine Instruction Bundle in LLVM
Hi all,
There have been quite a bit of discussions about adding machine instruction bundle to support VLIW targets. I have been pondering what the right representation should be and what kind of impact it might have on the LLVM code generator. I believe I have a fairly good plan now and would like to share with the LLVM community.
Design Criteria
1. The
2013 Jan 18
0
[LLVMdev] simple optimization question
Hi Bjorn,
> currently the following two lines of code with integer variables get compiled completely differently:
>
> if (d0<tmp) d0=tmp;
there must be something else going on because this
void bar(int);
void foo(int d0, int tmp) {
if (d0 < tmp) d0=tmp;
bar(d0);
}
when compiled like this
clang -S -O4 -o - sel.c
gives this
define void @foo(i32 %d0, i32 %tmp) nounwind