similar to: [LLVMdev] Backend calling convention: when pointer differs from integer

Hi, I am trying to complete the hardware multiplier option for MSP430 backend. As the hardware multiplier in most of the MSP430 devices is for i8 and i16 operands, with i16 and i32 result, I am lowering MUL_i8 and MUL_I16. However, the front-end promotes the i8 argument to i32, executes 32-bit multiplier and truncates to 16-bit, so I never lower MUL_I8 nor MUL_I16 but MUL_I32, wchich is lowered

Hi, I am creating a new backend for a custom microcontroller. In order to create the backend I am modifying from Mips backend. My architecture has a store instruction with direct address mode. It accepts two arguments: source register and address (immediate). This instruction is not available in Mips, but it is in Hexagon, so I copied from Hexagon the following, adapting it to my registers: -

Hi everyone, I am currently working on a backend for the TriCore architecture. Unfortunately, I have hit an issue with LLVM's internal representation that's giving me a bit of a headache. The problem is that LLVM assumes that a pointer is equivalent to a machine-word sized integer. This implies that all pointer arithmetic takes place in the CPU's general-purpose registers and is done

On Mon, Oct 8, 2012 at 2:44 AM, Pedro Malagón <malagon at die.upm.es> wrote: > Hi, > > I am trying to complete the hardware multiplier option for MSP430 backend. > > As the hardware multiplier in most of the MSP430 devices is for i8 and > i16 operands, with i16 and i32 result, I am lowering MUL_i8 and MUL_I16. > However, the front-end promotes the i8 argument to i32,

FYI, we are also interested. (But our limited staff are currently busy just getting our LLVM backend out of the door (in-house only). I hope we will have time to look at this in a year or so.) Regards, Patrik Hägglund -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Pedro Malagon Sent: den 3 december 2013 14:30 To: llvmdev at

I would also be interested in fixed-point arithmetic support in clang/llvm? Is there any movement on this direction since August? Regards, Pedro Malagon -- Pedro Malagon Dpt. Electrical Engineering - Technical University of Madrid Assistant Professor Office B-113 Avda. Complutense s/n, 28040 Madrid Tel. (+34) 915495700 ext. 4220 @:malagon at die.upm.es On 08/10/2013 09:24 PM, Giorgio

Hi - I wrapped R.dll up using somebody code online (see below). I am comparing R on .NET IPC with R(D)COM. I got it all working. Except, I realize that in my client code of the IPC remoting, if I call 'plot' function in R via EvaluateNoReturn, I don't seem to see any results on the R plot window (although the window pops up). Is there anything to do with the code of R.dll wrapper

After a long processing, I was able to create a version of a small C# class that was able to emulate the rproxy by P/Invoke. This is mostly to find a workaround a performance problem of the StatConnector. It's almost work but ... I have strange memory exception when I call the print function. The variable seems to not survive from one call to the other. As there is no debug symbol for

Hello Pedro, As others have said we're assuming that you're using Clang as the frontend, the MSP430TargetInfo class inside lib/Basic/Targets.cpp (clang codebase) set ints to be 16 bits wide, so you should get 16bit mults straight away without promotion. But anyways for 8bit multiplicantions you can do the following to bypass argument promotion: 1) go to the lib/CodeGen/TargetInfo.cpp

> At -O0, you don't. __mulsi3 is the obvious lowering, and you're doing > something wrong if your tools don't provide it. MSP430 is 16 bit target, so mulsi is a bit expensive there, mulhi / mulqi can be implemented via hardware multiplier. There are several problems wrt 16 bit support inside LLVM in general and msp430 in particular: 1. In some places LLVM expectes 32 bit or 64

On Tue, Aug 21, 2012 at 1:25 AM, Fabian Scheler <fabian.scheler at gmail.com> wrote: > 2012/8/20 Eli Friedman <eli.friedman at gmail.com>: >> On Mon, Aug 20, 2012 at 12:01 AM, Fabian Scheler >> <fabian.scheler at gmail.com> wrote: >>> Hi Eli, >>> >>>>>>> 2. Storing arbitrary sized integers >>>>>>>

Hi LLVM-Folks, at our department we have an in-house developed back-end for the TriCore processor and we want to upgrade it to LLVM 3.1. However, we have some troubles regarding some instructions that work on 64bit registers: The TriCore processor has 16 32bit registers that can be paired to form 64bit registers. Except a few instructions all work on 32bit registers, thus the TriCore processor

2012/8/20 Eli Friedman <eli.friedman at gmail.com>: > On Mon, Aug 20, 2012 at 12:01 AM, Fabian Scheler > <fabian.scheler at gmail.com> wrote: >> Hi Eli, >> >>>>>> 2. Storing arbitrary sized integers >>>>>> >>>>>> The testcase "test/CodeGen/Generic/APIntLoadStore.ll" checks for >>>>>>

Fabian, We have a very similar setup with the AMDIL backend(some operations support 64bit some don't). What we do is we enable MVT::i64, set legal to all operands that are legal and then set everything else to expand. Micah > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Fabian Scheler > Sent: Wednesday,

>> here are the definitions of these register classes: >> >> // Data register class >> def DR : RegisterClass<"TriCore", [i32], 32, >> (add D0, D1, D2, D3, D4, D5, D6, D7, >> D8, D9, D10, D11, D12, D13, D14, D15)>; >> >> // Extended-size data register class >> def ER :

On Mon, Aug 20, 2012 at 12:01 AM, Fabian Scheler <fabian.scheler at gmail.com> wrote: > Hi Eli, > >>>>> 2. Storing arbitrary sized integers >>>>> >>>>> The testcase "test/CodeGen/Generic/APIntLoadStore.ll" checks for >>>>> loading/storing e.g. i33 integers from/into global variable. The >>>>> questions

2012/8/22 Ivan Llopard <ivanllopard at gmail.com>: > Hi Fabian, Anton, > > > On 22/08/2012 08:25, Fabian Scheler wrote: >>>> >>>> here are the definitions of these register classes: >>>> >>>> // Data register class >>>> def DR : RegisterClass<"TriCore", [i32], 32, >>>>

Hi Eli, >>>> 2. Storing arbitrary sized integers >>>> >>>> The testcase "test/CodeGen/Generic/APIntLoadStore.ll" checks for >>>> loading/storing e.g. i33 integers from/into global variable. The >>>> questions are the same as regarding feature 1: How important is this >>>> feature? Is it save to ignore it? Is there

On 23/08/2012 11:06, Fabian Scheler wrote: > 2012/8/22 Ivan Llopard<ivanllopard at gmail.com>: >> Hi Fabian, Anton, >> >> >> On 22/08/2012 08:25, Fabian Scheler wrote: >>>>> here are the definitions of these register classes: >>>>> >>>>> // Data register class >>>>> def DR :

Hi Fabian, Anton, On 22/08/2012 08:25, Fabian Scheler wrote: >>> here are the definitions of these register classes: >>> >>> // Data register class >>> def DR : RegisterClass<"TriCore", [i32], 32, >>> (add D0, D1, D2, D3, D4, D5, D6, D7, >>> D8, D9, D10, D11, D12, D13, D14,