similar to: [LLVMdev] Handling Masked Vector Operations

Hi David, > > It seems the only solution is to create an intrinsic: > > llvm_int_load_masked mask, [addr] > > But this unnecessarily shuts down optimization. > I think that using intrinsics is the right solution. I imagine that most interesting load/store optimizations happen before vectorization, so I am not sure how much we can gain by optimizing masked load/stores.

Nadav Rotem <nrotem at apple.com> writes: > For DIV/MOD you can blend the inputs BEFORE the operation. You can > place ones or zeros depending on the operation. Quick follow-up on this. What about using "undef" as the input for false items: tv1 = select mask, v1, undef tv2 = select mask, v2, undef tv3 = div tv1, tv2 v3 = select mask, tv3, undef I'm always confused

Nadav Rotem <nrotem at apple.com> writes: > > For DIV/MOD you can blend the inputs BEFORE the operation. You > can > place ones or zeros depending on the operation. > > Quick follow-up on this. What about using "undef" as the input for > false items: > > tv1 = select mask, v1, undef > tv2 = select

> >> For DIV/MOD you can blend the inputs BEFORE the operation. You can >> place ones or zeros depending on the operation. > > Quick follow-up on this. What about using "undef" as the input for > false items: > > tv1 = select mask, v1, undef > tv2 = select mask, v2, undef > tv3 = div tv1, tv2 > v3 = select mask, tv3, undef > > I'm

Hi David, On 02/05/13 17:57, dag at cray.com wrote: > We're looking at how to handle masked vector operations in architectures > like Knight's Corner. In our case, we have to translate from a fully > vectorized IR that has mask support to llvm IR which does not have mask > support. > > For non-trapping instructions this is fairly straightforward: > > ; Input >

On 2 May 2013 16:57, <dag at cray.com> wrote: > We're looking at how to handle masked vector operations in architectures > like Knight's Corner. In our case, we have to translate from a fully > vectorized IR that has mask support to llvm IR which does not have mask > support. > Has anyone done a comparision between the "fully vectorized IR and "LLVM

Duncan Sands <baldrick at free.fr> writes: > there seems to be a plan to get rid of the select instruction and just use > branches and phi nodes instead. Amongst other things this requires boosting > the power of codegen so that branches+phi nodes can be turned into cmov or > whatever when appropriate. This is a very BAD idea. Are you telling me that every predicated

On Thu, May 2, 2013 at 10:31 AM, <dag at cray.com> wrote: > Nadav Rotem <nrotem at apple.com> writes: > > > > > For DIV/MOD you can blend the inputs BEFORE the operation. You > > can > > place ones or zeros depending on the operation. > > > > Quick follow-up on this. What about using "undef" as the input

v1 was: https://www.redhat.com/archives/libguestfs/2019-September/thread.html#00361 v2: - Adds a patch to rename the reflection plugin to the info plugin. - Adds tests. Rich.

I'm trying to understand how predicated/masked instructions can be generated in llvm, specifically an instruction where a set bit in the mask will write the new result into the corresponding vector lane in the destination and a clear bit will cause the lane in the destination to remain what it was before the instruction executed. I've seen a few places that suggest 'select' is the

Dan Gohman <dan433584 at gmail.com> writes: > And, in part because a popular trend seems to be to have SIMD units > which don't trap or raise exception flags on arithmetic and which don't > go faster when predicated, such that there's no  reason to predicate > anything except stores and occasionally loads. On these architectures, > simply having intrinsics for

On Thu, 31 Jan 2019 at 20:17, Philip Reames via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > On 1/31/19 11:03 AM, David Greene wrote: > > Philip Reames <listmail at philipreames.com> writes: > > > >> Question 1 - Why do we need separate mask and lengths? Can't the > >> length be easily folded into the mask operand? > >> >

Hi, There is now an RFC for a roadmap to native vector predication support in LLVM and a prototype implementation:   https://reviews.llvm.org/D57504 The prototype demonstrates: -  Predicated vector intrinsics with an explicit mask and vector length parameter on IR level. -  First-class predicated SDNodes on ISel level. Mask and vector length are value operands. -  An incremental strategy

On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote: > Jeff Bush <jeffbush001 at gmail.com> writes: > >> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...> >> %ty = select %mask, %y, <0.0, 0.0, 0.0 ...> >> %sum = fadd %tx, %ty >> %newvalue = select %mask, %sum, %oldvalue >> >> I believe the generated instructions depend on whether

Philip Reames <listmail at philipreames.com> writes: > Question 1 - Why do we need separate mask and lengths? Can't the > length be easily folded into the mask operand? > > e.g. newmask = (<4 x i1>)((i4)%y & (1 << %L -1)) > and then pattern matched in the backend if needed I'm a little concerned about how difficult it will be to maintain enough

I want to compare two documents in the index (i.e. retrieve the cosine similarity/score between two documents term-vector''s). Is this possible using the standard Ferret functionality? Thanks in advance, Jeroen Bulters -- Posted via http://www.ruby-forum.com/.

On May 6, 2013, at 9:35 AM, dag at cray.com wrote: >>> It's easy enough to write a TableGen pattern to match add+select and >>> emit a masked instruction. Alternative, we can always resort to manual >>> lowering (ugh). >>> >>> For trapping operations this is problematic. Take a load. Here's the >>> same attempt with a load:

On Oct 22, 2012, at 10:15 AM, dag at cray.com wrote: > > It's true that a target-independent predicated IR isn't going to > translate well to a target that doesn't have predication. However, for > targets that do it's a godsend. Even for MIC (Xeon Phi), the predicated IR is not necessary. The instructions that really benefit from predication are loads and stores.

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