Displaying 20 results from an estimated 3000 matches similar to: "[LLVMdev] Floating-point FABS - supporting"
2016 Jun 14
2
llvm intrinsics/libc/libm question
If I do
T.getArch() == xxx
TLI.setUnavailable(LibFunc::copysign)
then this works at generating a call instead of not being able to select
the ISD::FCOPYSIGN, but I don't know why I don't need to do this for other
LibFunc functions (such as floor, etc... these generate call just fine)?
Thanks,
Ryan
On Tue, Jun 14, 2016 at 11:58 AM, Ryan Taylor <ryta1203 at gmail.com> wrote:
2016 Jun 07
2
llvm intrinsics/libc/libm question
Tim,
Are you referring to setLibcallName? That is target specific yes but there
isn't RTLIB for most of the libm functions, for example, for acos this
doesn't apply.
Ideally what I would like is to create a libc with functions like acos
called something like __xxx_acos that can still be recognized to be
optimized.
RTLIB is pretty limited but it works fine, I can just use
2016 Jun 07
4
llvm intrinsics/libc/libm question
On Tue, Jun 7, 2016 at 1:57 PM, Ryan Taylor <ryta1203 at gmail.com> wrote:
> Tim,
>
> Currently, I have to do multiple things:
>
> 1) create some setLibcallNames in XXXISelLowering.cpp to generate correct
> naming for RTLIBS.
> 2) lower ISD down to an RTLIB for some calls (and then do solution 1 on
> those to get correct names)
These solve a related but different -
2014 Apr 15
2
[PATCH 2/3] Use fabsf() instead of fabs() since we have floats, not double
On Tue, Apr 15, 2014 at 12:33 PM, Peter Meerwald <pmeerw at pmeerw.net> wrote:
> Signed-off-by: Peter Meerwald <pmeerw at pmeerw.net>
> ---
> libspeexdsp/resample.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/libspeexdsp/resample.c b/libspeexdsp/resample.c
> index e32ca45..a19b997 100644
> ---
2017 Mar 09
2
Help understanding and lowering LLVM IDS conditional codes correctly
On Thu, Mar 9, 2017 at 9:35 PM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> On 02/25/2017 03:06 AM, vivek pandya via llvm-dev wrote:
>
> Note: Question is written after describing what I have coded.
>
> Hello LLVMDevs,
>
> I am trying to impliment floating point comparsion for an architecture
> which
> supports following type of floating point comparision if FPU
2017 Mar 14
2
Help understanding and lowering LLVM IDS conditional codes correctly
On 03/14/2017 07:16 AM, vivek pandya wrote:
> Hello Hal,
> setCondCodeAction(expand) for un ordered comparison generates
> semantically wrong code for me for example SETUNE gets converted to
> SETOE that causes infinite loops.
Can you please explain what is happening? It sounds like a bug we should
fix.
>
> What is ideal place where I can convert unordered comparison to un
2017 Feb 25
2
Help understanding and lowering LLVM IDS conditional codes correctly
Note: Question is written after describing what I have coded.
Hello LLVMDevs,
I am trying to impliment floating point comparsion for an architecture which
supports following type of floating point comparision if FPU is available:
fcmp.un --> true if one of the operand is NaN
fcmp.lt --> ordered less than, if any input NaN then return false
fcmp.eq --> ordered equal, if any input NaN
2014 Apr 15
0
[PATCH 2/3] Use fabsf() instead of fabs() since we have floats, not double
Signed-off-by: Peter Meerwald <pmeerw at pmeerw.net>
---
libspeexdsp/resample.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/libspeexdsp/resample.c b/libspeexdsp/resample.c
index e32ca45..a19b997 100644
--- a/libspeexdsp/resample.c
+++ b/libspeexdsp/resample.c
@@ -85,7 +85,7 @@ static void speex_free (void *ptr) {free(ptr);}
#ifdef FIXED_POINT
#define
2013 May 06
1
[LLVMdev] Help with setting up a software-float supported architecture target
For a LLVM code target, I am developing a software-supported floating-point
engine. I've come into a few issues in which the DAG conversion is
Can anyone help with:
I have some C code test like:
float x;
printf("%f", x);
which clang coverts to:
%0 = load float* @x, align 4
%conv = fpext float %0 to double
The issue is for simple Float to Double extension, the DAGCombiner.cpp
2018 Aug 02
1
[PATCH 1/2] Add fabs() implementation
When we add -ffreestanding the compiler won't get to inline this any more.
Signed-off-by: David Woodhouse <dwmw2 at infradead.org>
---
com32/lib/math/fabs.S | 15 +++++++++++++++
mk/lib.mk | 2 +-
2 files changed, 16 insertions(+), 1 deletion(-)
create mode 100644 com32/lib/math/fabs.S
diff --git a/com32/lib/math/fabs.S b/com32/lib/math/fabs.S
new file mode 100644
index
2017 Oct 07
2
Bug 20871 -- is there a fix or work around?
Ignore the suggested fix in my earlier post. How about this?
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 20c81c3..b8ebf42 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1632,10 +1632,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
if (!Subtarget.is64Bit()) {
// These
2005 Apr 28
3
[LLVMdev] Floating point instructions patch
Hello,
I have been gone for a while, finishing work on my Master's thesis... Now that I'm back I updated LLVM to the most
recent version and found that my FP_ABS SelectionDAGNode type and code generation was now conflicting with the new FABS
node type. I brought the rest of my local modifications in line with the FABS implementation, so here is my patch that
includes sqrt, sin and cos
2005 Apr 28
0
[LLVMdev] Floating point instructions patch
On Thu, 28 Apr 2005, Morten Ofstad wrote:
> I have been gone for a while, finishing work on my Master's thesis...
Hi Morten, congrats! :)
> Now that I'm back I updated LLVM to the most recent version and found
> that my FP_ABS SelectionDAGNode type and code generation was now
> conflicting with the new FABS node type. I brought the rest of my local
> modifications in
2019 Jun 10
2
Bug: Library functions for ISD::SRA, ISD::SHL, and ISD::SRL
LLVM appears to support Library functions for ISD::SRA ,ISD::SHL, and ISD::SRL, as they are properly defined in RuntimeLibCalls.def.
The library functions defined in RuntimeLibCalls.def (among others) are these:
HANDLE_LIBCALL(SRA_I16, "__ashrhi3")
HANDLE_LIBCALL(SRA_I32, "__ashrsi3")
HANDLE_LIBCALL(SRA_I64, "__ashrdi3")
However, setting
2013 Jul 30
3
[LLVMdev] Help with promotion/custom handling of MUL i32 and MUL i64
I'll try to run through the scenario:
64-bit register type target (all registers have 64 bits).
all 32-bits are getting promoted to 64-bit integers
Problem:
MUL on i32 is getting promoted to MUL on i64
MUL on i64 is getting expanded to a library call in compiler-rt
the problem is that MUL32 gets promoted and then converted into a
subroutine call because it is now type i64, even though
2018 Jul 02
2
[RFC][VECLIB] how should we legalize VECLIB calls?
Adding to Ashutosh's comments, We are also interested in making LLVM
generate vector math library calls that are available with glibc (version >
2.22).
reference: https://sourceware.org/glibc/wiki/libmvec
Using the example case given in the reference, we found there are 2 vector
versions for "sin" (4 X double) with same VF namely _ZGVcN4v_sin (avx)
version and _ZGVdN4v_sin
2018 Jul 02
2
[RFC][VECLIB] how should we legalize VECLIB calls?
It may not be a full solution for the problems you're trying to solve, but
I don't know why adding to include/llvm/CodeGen/RuntimeLibcalls.def is a
problem in itself. Certainly, it's a mess that could be organized,
especially so we're not repeating everything for each data type as we do
right now.
So yes, I think that would allow us to remove the VecLib mappings because
we are
2014 Feb 05
2
[LLVMdev] Using Compiler-RT with Clang on ARM
Hi Daniel,
I'm trying to use the feature you added to Clang a long time ago (2011),
the --rtlib=compiler-rt and it doesn't seem to do anything.
Now that I have compiler-rt building on ARM and the archive libraries under
/lib, I'd like to replace -lgcc with -lclang_rt, but this command line:
$ clang --rtlib=compiler-rt -Wl,-lclang_rt foo.c
Gives me the warning/errors:
clang-3.5:
2012 Jan 07
2
[LLVMdev] libcalls for shifts
Hello,
my target has libcall support for long long shifts. I already have the
following lines in my Lowering constructor:
setLibcallName(RTLIB::SHL_I64, "__llshl");
setLibcallName(RTLIB::SRL_I64, "__llshru");
setLibcallName(RTLIB::SRA_I64, "__llshr");
and
setOperationAction(ISD::SHL, MVT::i64, Expand);
setOperationAction(ISD::SRA, MVT::i64,
2014 Oct 22
3
[LLVMdev] LibUnwind into Compiler-RT?
On 22 October 2014 19:24, Jonathan Roelofs <jonathan at codesourcery.com> wrote:
> I do compiler_rt + libc++abi + libc++ + clang (with a custom ToolChain) testing
> of libc++ on bare-metal ARM.... so it is possible. Perhaps you mean to say that
> it's not possible to test libunwind on arm-linux when using compiler_rt?
Yeah, it's hard and clumsy, not impossible.
Basically,