similar to: [LLVMdev] Help with setting up a software-float supported architecture target

On 7/19/10 10:36 AM, Duncan Sands wrote: > Hi JP, > > >> DAGCombiner::ReduceLoadWidth() does the following: >> /// ReduceLoadWidth - If the result of a wider load is shifted to right of N >> /// bits and then truncated to a narrower type and where N is a multiple >> /// of number of bits of the narrower type, transform it to a narrower load >> /// from

I've isolated a bug in SSE codegen to the attached example. define void @f(<2 x float>* %in, <2 x double>* %out) { entry: %0 = load <2 x float>* %in, align 8 %1 = fpext <2 x float> %0 to <2 x double> store <2 x double> %1, <2 x double>* %out, align 1 ret void } The code should load a <2 x float> vector from %in, fpext cast it to

I would like to revive this thread, as I am struggling a lot with the FP16 implementation in the ARM backend. My implementation in https://reviews.llvm.org/D38315 is finished (except one case), but a more robust alternative implementation was suggested. One can indeed argue that my current implementation is a bit fragile, because it involves manually patching up the isel dags for a few cases. The

On Wed, May 20, 2009 at 5:26 PM, Eli Friedman <eli.friedman at gmail.com> wrote: > On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: >> Can you explain why you chose the approach of using a new pass? >> I pictured removing LegalizeDAG's type legalization code would >> mostly consist of finding all the places that use TLI.getTypeAction

Hi Arsen, On Oct 9, 2013, at 4:53 AM, Arsen Hakobyan <artinetstudio at gmail.com> wrote: > Hi all, > > I have the following test case: > #define FLT_EPSILON 1.19209290E-7 > > int err = -1; > int main() > { > float a = 8.1; > if (((a - 8.1) >= FLT_EPSILON) || ((a - 8.1) <= -FLT_EPSILON)) { //I am > using FLT_EPSILON to check whether (a != 2.0).

Trying to import a bunch of data files named like f001, f002, ....f999. Some of the files may be missing and the missing files vary from time to time. Used for loop and read.table. When it reaches the missing file (say f100), it shows: Error in file(file, "r") : cannot open the connection In addition: Warning message: In file(file, "r") : cannot open file 'f100': No

Hi JP, > DAGCombiner::ReduceLoadWidth() does the following: > /// ReduceLoadWidth - If the result of a wider load is shifted to right of N > /// bits and then truncated to a narrower type and where N is a multiple > /// of number of bits of the narrower type, transform it to a narrower load > /// from address + N / num of bits of new type. If the result is to be > /// extended,

Hi all, I have the following test case: #define FLT_EPSILON 1.19209290E-7 int err = -1; int main() { float a = 8.1; if (((a - 8.1) >= FLT_EPSILON) || ((a - 8.1) <= -FLT_EPSILON)) { //I am using FLT_EPSILON to check whether (a != 2.0). err = 1; } else { err = 0; } return 0; } with -O3 optimization level clang generates already incorrect LLVM IR: ; Function Attrs:

Hi Sjoerd, For ISel, I think having a separate register class will give you less headache. I wondering if you could get away with not touching the instructions descriptions at all, instead defining external pattens for the FullFP16 case, like so: def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), IIC_fpCVTSH, "vcvtb",

I have a simple test case that my code generator handles fine when using optimizations, but when I disable optimizations, It turns into a sequence of instructions that I can't figure out what to setup to get it to generate the correct code. The instructions in question are: %tmp1 = load float* %test ; <float> [#uses=1] %conv = fpext float %tmp1 to double ;

Hi, The target I am working on does not support i8 loading: it supports only 32 bit aligned loads. I had to custom lower i8 load so that only i32 loads are generated. My issue is the following: In a very specific case, the lowering stage generates the following pattern where the load is a i32 load: (and (load x), 255) This pattern is somehow converted by the DAG combiner back to: (zextload x,

On Thu, Sep 08, 2011 at 11:15:06AM -0500, Villmow, Micah wrote: > Peter, > Is there a way to make this flag globally available? Metadata can be fairly expensive to handle at each node when in many cases it is a global flag and not a per operation flag. There are two main reasons why I think we shouldn't go for global flags: 1) It becomes difficult if not impossible to correctly link

On Mon, Jul 18, 2011 at 6:35 PM, Damien Vincent <damien.llvm at gmail.com> wrote: > >   Hi, > > The target I am working on does not support i8 loading: it supports only 32 > bit aligned loads. > I had to custom lower i8 load so that only i32 loads are generated. > > My issue is the following: > In a very specific case, the lowering stage generates the following

I'm curious about this code in ReduceLoadWidth (and in DAGCombiner in general): if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) return SDValue <http://llvm.org/docs/doxygen/html/classllvm_1_1SDValue.html>(); LegalOperations is false for the first pre-legalize pass and true for the post-legalize pass. The first pass is target-independent yes? So that makes sense.

On Sun, 25 Feb 2007, Nicolas Geoffray wrote: > No problem. Plus the reviewing may have taken some time. So thx a lot > for committing. I talked to Jim who said > he wanted to commit his changes before mine -- I hope everything's Ok. There is one significant bug that fell out from this, which caused some macho function calls to be compiled with ELF ABI semantics. I checked in this

For the following C code __fp16 x, y, z, w; void foo() { x = y + z; x = x + w; } clang produces IR that extends each operand to float and then truncates to half before assigning to x. Like this define dso_local void @foo() #0 !dbg !18 { %1 = load half, half* @y, align 2, !dbg !21 %2 = fpext half %1 to float, !dbg !21 %3 = load half, half* @z, align 2, !dbg !22 %4 = fpext half %3 to float, !dbg

Hi, I am working on C/C++ language support for the Armv8.2-A half-precision instructions. I've added support for _Float16 as a new source language type to Clang. _Float16 is a C11 extension type for which arithmetic is well defined, as opposed to e.g. __fp16 which is a storage-only type. I then fixed up the AArch64 backend, which was mostly straightforward: this involved making operations

Thanks Eli. I forgot to bring up the strict FP questions which I was working on when I found this. If we're in a strict FP function, do the fp_to_f16/f16_to_fp emitted by promoting load/store/bitcast need to be strict versions of fp_to_f16/f16_to_fp. And if so where do we get the chain, especially for the bitcast case which isn't a chained node. ~Craig On Tue, Dec 10, 2019 at 3:18 PM

Hello, I have a remote IBM x3550 M4 server that I try to remote control through IMM2. The problem: only the blinking cursor is visible in login console. It moves when I type. It moves to where "Login: _" should be if I press ctrl+c. I can login if I enter the correct login and password, but the shell that I get also shows only the blinking cursor and no text. I can issue commands.

Hi Matthias, what I’m observing right now is that replacing opt+llc with an clang invocation, and subsequently fewer intermediate files, increases the consumed time with -O0 by 200%. We used to always run opt with -mem2reg -globalopt, and I believe those are not part of -O0 (is there an easy way to list all passes that -OX flags to clang imply for the optimizer and code gen?). Could the IR imply