similar to: [LLVMdev] buildbot failure in LLVM on llvm-ppc64-linux1

Displaying 20 results from an estimated 1000 matches similar to: "[LLVMdev] buildbot failure in LLVM on llvm-ppc64-linux1"

2015 Jun 10
2
[LLVMdev] Why buildbot sanitizer-ppc64-linux1 blames r239459?
I'm trying to understand why the buildbot sanitizer-ppc64-linux1 fails due to my latest patch. It was in llvm::GlobalValue while the reported failure is: strcspn-2.c.tmp: /home/buildbots/sanitizerslave1/sanitizer-ppc64-1/build/llvm/projects/compiler-rt/test/asan/TestCases/strcspn-2.c:17: int main(int, char **): Assertion `r == sizeof(s1) - 1' failed. where strcspn-2.c (below) tests the
2012 Aug 28
0
[LLVMdev] TableGen backend support to express relations between instruction
Jyotsna, I hadn't been following this, so I apologize if this has already been provided, but can you give a quick example of how this functionality is used? Thanks in advance, Hal On Tue, 28 Aug 2012 13:01:17 -0500 "Jyotsna Verma" <jverma at codeaurora.org> wrote: > Hi Jakob, > > Here is the first draft of the patch to add TableGen backend support > for the
2012 Aug 28
1
[LLVMdev] TableGen backend support to express relations between instruction
Hi Hal, I will try to explain the functionality using a simple example. Let's say that we have three formats for 'ADD' instruction and we want to relate them. ADD - non-predicated form ADD_pt : predicate true ADD_pf : predicate false We can define the relationship between the non-predicated instructions and their predicate formats as follows: def getPredOpcode : InstrMapping { //
2012 Aug 31
0
[LLVMdev] TableGen backend support to express relations between instruction
Hi Jakob, Did you get a chance to look at the patch? Thanks, Jyotsna -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Jyotsna Verma Sent: Tuesday, August 28, 2012 1:01 PM To: 'Jakob Stoklund Olesen' Cc: llvmdev at
2013 Mar 11
0
[LLVMdev] Disabling ExecutionEngine tests for Hexagon
Hi Jyotsna, Currently there's a preprocessor trick that prevents llvm/unittests/ExecutionEngine/MCJIT tests from running on architectures and operating systems that are known to fail. Specifically, check out the functions OSSupportsMCJIT() and ArchSupportsMCJIT() functions in unittests/ExecutionEngine/MCJIT/MCJITTestBase.h, and the corresponding macro SKIP_UNSUPPORTED_PLATFORM that is used
2013 Mar 12
2
[LLVMdev] Disabling ExecutionEngine tests for Hexagon
Thanks Dan! The ArchSupportMCJIT() functions in unittests/ExecutionEngine/MCJIT/MCJITTestBase.h uses "Host Triple" to check for compatibility. Since we cross-compile on X86, "Host Triple" for us will be "X86" which is a supported architecture. I tried removing it from the supported arch list but didn't see any effect. I was just wondering if these tests are
2012 Aug 20
2
[LLVMdev] TableGen related question for the Hexagon backend
You're right. I can have use RowFields for that purpose. Thanks, Jyotsna -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. -----Original Message----- From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] Sent: Monday, August 20, 2012 3:42 PM To: Jyotsna Verma Cc: 'Tony Linthicum'; llvmdev at cs.uiuc.edu Subject: Re: TableGen related question for the Hexagon
2012 Aug 21
0
[LLVMdev] TableGen related question for the Hexagon backend
Jakob, One more question. You had suggested 'ValueCols' as of type list<list<string> >. Does the TableGen know how to extract it? It appears to me that we may have to add support for that. Thanks, Jyotsna -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at
2012 Aug 28
4
[LLVMdev] TableGen backend support to express relations between instruction
Hi Jakob, Here is the first draft of the patch to add TableGen backend support for the instruction mapping tables. Please take a look and let me know your suggestions. As of now, I create one mapping table per relation which results into a long .inc file. So, I'm planning to combine everything into a single table and will include APIs (one per relation) to query from this table. Thanks,
2013 Mar 13
0
[LLVMdev] Disabling ExecutionEngine tests for Hexagon
On 2013-03-13 3:15 AM, "Jyotsna Verma" <jverma at codeaurora.org> wrote: > >I noticed "TARGET_HAS_JIT" flag in Makefile.config. Can I use this flag to >exclude MCJIT and JIT tests when not set? This will be a simpler change >than >modifying the macro. > >Thanks, >Jyotsna TARGET_HAS_JIT seems to be an autoconf thing (also, not really sure how it
2015 Oct 29
2
Fwd: buildbot failure in LLVM on sanitizer-ppc64-linux1
This long running bot failed on a unused variable warning. Given that several other bots cover the warnings, any chance we could get this one configured to not fail the build on warnings? Doing so would make it more likely to actually get to the "sanitizer" part of the testing process. Philip -------- Forwarded Message -------- Subject: buildbot failure in LLVM on
2012 Aug 21
1
[LLVMdev] TableGen related question for the Hexagon backend
On Aug 20, 2012, at 9:22 PM, Jyotsna Verma <jverma at codeaurora.org> wrote: > Jakob, > > One more question. You had suggested 'ValueCols' as of type > list<list<string> >. Does the TableGen know how to extract it? It appears to > me that we may have to add support for that. You just start from getValueAsListInit() and go from there. /jakob
2012 Aug 20
0
[LLVMdev] TableGen related question for the Hexagon backend
On Aug 20, 2012, at 1:32 PM, "Jyotsna Verma" <jverma at codeaurora.org> wrote: > In the Hexagon backend, a predicated instruction can translate into another > form called 'predicate new'. So, in our example of 'ADD', we can have > another transformation like this - > > ADD--- ---> ADDtrue -----> ADDtru_new (predicate new form of true) >
2019 Oct 24
2
Failed PPC64 compile when using Power7 loads and stores?
Hi Everyone, I'm having trouble figuring out a compile failure on ppc64le. The failure is at https://travis-ci.org/noloader/cryptopp-autotools/jobs/602187190 . The message is: /bin/bash ./libtool --tag=CXX --mode=compile clang++ -DHAVE_CONFIG_H -I. -DCRYPTOPP_DISABLE_POWER8 -pipe -mcpu=power7 -mvsx -maltivec -g -O2 -MT libppc_power7_la-ppc_power7.lo -MD -MP -MF
2012 Aug 16
2
[LLVMdev] TableGen related question for the Hexagon backend
Hi Everyone, After some more thoughts to the Jacob's suggestion of using multiclasses for Opcode mapping, this is what I have come up with. Please take a look at the design below and let me know if you have any suggestions/questions. I have tried to keep the design target independent so that other targets could benefit from it. 1) The idea is to add 3 new classes into
2012 Aug 17
0
[LLVMdev] TableGen related question for the Hexagon backend
On Aug 16, 2012, at 1:39 PM, Jyotsna Verma <jverma at codeaurora.org> wrote: > Hi Everyone, > > After some more thoughts to the Jacob's suggestion of using multiclasses for > Opcode mapping, this is what I have come up with. Please take a look at the > design below and let me know if you have any suggestions/questions. Hi Jyotsna, You are on to something here, but you
2013 Mar 12
0
[LLVMdev] Disabling ExecutionEngine tests for Hexagon
On 2013-03-12 1:28 AM, "Jyotsna Verma" <jverma at codeaurora.org> wrote: >Thanks Dan! > >The ArchSupportMCJIT() functions in >unittests/ExecutionEngine/MCJIT/MCJITTestBase.h uses "Host Triple" to >check >for compatibility. Since we cross-compile on X86, "Host Triple" for us >will >be "X86" which is a supported architecture. I
2012 Aug 02
0
[LLVMdev] TableGen related question for the Hexagon backend
On Aug 1, 2012, at 1:53 PM, Jyotsna Verma <jverma at codeaurora.org> wrote: > > Currently, we rely on switch tables to transform between formats. However, > we would like to have a different mechanism to represent these relationships > instead of switch tables. I am thinking of modeling these relations in > HexagonInstrInfo.td file and use TableGen to generate a table with
2014 Mar 26
2
[LLVMdev] PPC64 buildbot
Hi, I just realised that the PPC64 bulddbot is failing because of a rather stupid issue: http://lab.llvm.org:8011/builders/llvm-ppc64-linux1 Just removing the additional assembly file would make it green again. ;) cheers, --renato
2002 Feb 18
1
VM_GROWSDOWN problem on S/390
We're running Samba 2.2.2 on an S/390 mainframe and have been experiencing problems with Samba seeming to access an invalid memory location. Below is part of the message log: Feb 15 10:48:38 linux1 kernel: VM_GROWSDOWN not set, but address 0 Feb 15 10:48:38 linux1 kernel: not in vma 0106a960 (start 400000 end 53A000) Feb 15 10:48:38 linux1 kernel: User process fault: