similar to: [LLVMdev] Define Integer to be of 2 Bytes for a Target

Hi Hal, Our Architecture has indirect move instruction which increments the pointer implicitly and the target only has i8 type values. So the load of i16 will be converted to two i8 target loads wherein after the first load instruction, the pointer to the first i8 address will automatically increment to point to the next i8 value. So the post increment nature is in the Target. A normal

Hi Hal, On Tuesday 01 October 2013 06:22 PM, Hal Finkel wrote: > ----- Original Message ----- >> Hi Hal, >> >> >> Our Architecture has indirect move instruction which increments >> the >> pointer implicitly and the target only has i8 type values. So the >> load >> of i16 will be converted to two i8 target loads wherein after the

----- Original Message ----- > Hi Hal, > > > Our Architecture has indirect move instruction which increments > the > pointer implicitly and the target only has i8 type values. So the > load > of i16 will be converted to two i8 target loads wherein after the > first > load instruction, the pointer to the first i8 address will > automatically >

Hi, We have an architecture where the indirect move instruction implicitly increments the pointer value after the move. We have Instruction format and pattern for this type of instructions. How to encode the information that the pointer is incremented? Thanks and regards, Shashidhar

----- Original Message ----- > Hi, > > We have an architecture where the indirect move instruction > implicitly increments the pointer > value after the move. We have Instruction format and pattern for this > type of instructions. > > How to encode the information that the pointer is incremented? As you seem to be aware, LLVM has patterns specifically to match

Hi Everyone, I am Shashidhar G, M.S. Research Scholar at Indian Institute of Technology Madras working in the area of Program Analysis and Compiling for Parallelization. I am interested in working with the LLVM community for GSOC 2016. I looked at the Open projects and i am interested to work in the area of Alias Analysis. I have implemented a simple version of Andersen's Analysis as LLVM

Shashidhar, Here's it for 32 and 64 bits. https://developer.apple.com/library/mac/#documentation/DeveloperTools/Conceptual/LowLevelABI/130-IA-32_Function_Calling_Conventions/IA32.html#//apple_ref/doc/uid/TP40002492-SW4 https://developer.apple.com/library/mac/#documentation/DeveloperTools/Conceptual/LowLevelABI/140-x86-64_Function_Calling_Conventions/x86_64.html -Dmitry. On Tue, Feb 26,

Hello, I am Shashidhar SR Working for Siemens Communication Software in Bangalore, INDIA as a Configuration Manager for Clearcase. I need some help regarding the samba configuration at our site. First Let me Explain our Environment: - We are Using samba 2.2.8a on Solaris 9. - We are using samba as an interop from Solaris 9 box to winnt/w2k/win-xp clients. - On Solaris we have installed IBM

Hi All, I am looking for a ABI Documentation of the X86 architecture to understand how LLVM converts its IR to X86 target instructions. Please guide me from where i can get the resources. Thanks, Shashidhar -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130226/05855007/attachment.html>

> > At first I thought this could be handled when lowering > loads and stores, but I realize that I can only catch the > targeted addresses of loads/stores here - however address > calculation nodes may occur anywhere in a DAG. > > > > So my first impulse would be to adjust the constants when > the GEP instructions are transformed to ADDs. Afaics his > would mean

On Jan 2, 2012, at 10:00 AM, Duncan Sands <baldrick at free.fr> wrote: > Hi Matt, > >> It seems that one of the optimization passes (it seems to be SROA) sometimes transforms computations on vectors of ints to computations on wide integer types; for example, I'm seeing code like the following after optimizations(*): >> >> %0 = bitcast<16 x i8>

It seems that one of the optimization passes (it seems to be SROA) sometimes transforms computations on vectors of ints to computations on wide integer types; for example, I'm seeing code like the following after optimizations(*): %0 = bitcast <16 x i8> %float2uint to i128 %1 = shl i128 %0, 8 %ins = or i128 %1, 255 %2 = bitcast i128 %ins to <16 x i8> The back end I'm

Hi, If I define a intrinsic function with pointer-typed parameter, for example, def llvm_foo_ptr_ty : LLVMPointerType<llvm_i16_ty>; def int_foo_get : Intrinsic<[llvm_foo_ptr_ty], [llvm_foo_ptr_ty, llvm_i32_ty], [IntrReadArgMem]>; How to lower it for the backend? I'm not sure what kind of register (i16 or i32 or i32) is needed in this case? If the parameter is

Hey again, I have a nagging thought that my past comments may not have enough meat to them. So... On Mon, Apr 8, 2013 at 12:01 PM, Cameron McInally <cameron.mcinally at nyu.edu>wrote: ... > I was just writing Chandler about a similar implementation. With my > current understanding of the problem, my constant division will end up as > either a trap call or a load of an undefined

Going that route, and with 64 bit processors picking up, I'm sure soon we will have to add two more new attributes: sign_ext_from_i32 and zero_ext_from_i32 which makes the number of attributes 8 (i1,i8,i16,i32) rather than 4 (i8,i16) Is this exactly what is desired? From one perspective it is good because it doesn't require too much modification. On the other hand the way that attributes

Hi list, I am in the process of creating a new target in LLVM/Clang for a custom 16-bit machine. My initial goal is to configure Clang so that when LLVM bytecode (or assembly) is generated, the integer size is 16 bits. After defining an appropriate TargetInfo subclass (where integer size is set to 16) the generated LLVM assembly looks almost correct, however one of the parameters for

On Thu, Feb 2, 2012 at 12:25 PM, Umesh Kalappa <umesh.kalappa0 at gmail.com> wrote: > Hi There , > > Again ,I'm newbie to LLVM  and please pardon me ..if you guys  feel that > ,the below question is very basic :) > > Here i go ,compiled the below sample with clang i.e clang enum.c -S > -emit-llvm and there respective file are > > $ cat enum.c > int main()

My two-address target machine has sign-extension instructions to extend i8->i32 and i16->i32. When I compile this simple program: int sext (unsigned a, unsigned b, int c) { return (signed char) a + (signed short) b + c; } I get this IR: define i32 @sext(i32 %a, i32 %b, i32 %c) nounwind readnone { entry: %conv = trunc i32 %a to i8 ; <i8>

Is there any way to keep pointer and integer register classes separate? My target has two 16-bit registers that can be used to contain address of data in register indirect addressing mode. I want to specify a register class for 16-bit pointer registers so that these registers can be allocated to pointers , at the same time I want all other interger operations to be expanded to 8-bit operations. If

Hi All, I have a C code: ////////////////////////////// #include "stdio.h" int main () { putchar('a'); return 0; } llvm-gcc -emit-llvm, I got //////////////////////////////////////// ; ModuleID = 't1.bc' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" target triple