similar to: [LLVMdev] New Register allocation algorithm

Hi, I wanted to write a new register allocation algorithm. I wrote it the same way RegAllocFast has been written and registered it. I added it to ForceCodegenLinking struct as well. But after build, it is not listed in llc --help. I tried to change the registered name of greedy algorithm to something else and that doesnt seem to be reflecting in llc help either. Am i supposed to build llvm

Just a quick question: is greedy still a local allocator (i.e. only takes into consideration the current bb) or a global one (takes into consideration the whole function)? -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110926/d87aa2bd/attachment.html> -------------- next part -------------- A non-text

On Sep 28, 2011, at 3:08 PM, Chris Lattner wrote: > > On Sep 27, 2011, at 12:11 AM, Leo Romanoff wrote: > >> >> >> It is true that names are not always reflecting the essense. But on the other hand, there is a lot of ongoing research on register allocation (and compilers in general) and it looks like more and more such efforts choose LLVM as a platform for

On Sep 27, 2011, at 12:11 AM, Leo Romanoff wrote: > > > It is true that names are not always reflecting the essense. But on the other hand, there is a lot of ongoing research on register allocation (and compilers in general) and it looks like more and more such efforts choose LLVM as a platform for experimentation. Quite some results and comparisons are published. So, it would be nice

Hi Jakob, Hi Andy, First of all, thanks a lot for very elaborative and interesting answers! > It may be more helpful to explain how LLVM's register allocator came > into existence before debating the high level algorithm. > > When I began working on LLVM last October, Jakob was developing an > infrastructure for global live range splitting. It was just becoming > clear

On Thu, 2010-06-03 at 02:53 +0200, Jakob Stoklund Olesen wrote: > If you are using the local register allocator, please try switching to the fast allocator and report any bugs you find. > Tried it, and it seems to break quite a big chunk of our tests on SPU :) Before r103488 ("Mostly rewrite RegAllocFast") there was no problem. But with r103488, I get a:

I'm getting this error in RegAllocFast.cpp in compiling one source file in test-suite as the result of a new Mips fast-isel patch I was testing. It apparently just generates bad code and continues? // Nothing we can do. Report an error and keep going with a bad allocation. if (MI->isInlineAsm()) MI->emitError("inline assembly requires more registers than

On Oct 28, 2010, at 9:40 AM, Jeff Kunkel wrote: > I have noticed quite a few changes regarding register allocation. I am > wondering will there be support for radically different data > structures other than the LiveIntervals, Virtual Register Map, etc? Not any more than we already have. If anything, these data structures are going to be simplified. For instance, VirtRegMap's

On 12/14/2017 10:18 PM, Leslie Zhai wrote: > Hi GCC and LLVM developers, > > I am learning Register Allocation algorithms and I am clear that: > > * Unlimited VirtReg (pseudo) -> limited or fixed or alias[1] PhysReg > (hard) > > * Memory (20 - 100 cycles) is expensive than Register (1 cycle), but > it has to spill code when PhysReg is unavailable > It might be

On Jun 4, 2010, at 1:57 AM, <Kalle.Raiskila at nokia.com> <Kalle.Raiskila at nokia.com> wrote: > On Thu, 2010-06-03 at 02:53 +0200, Jakob Stoklund Olesen wrote: >> If you are using the local register allocator, please try switching to the fast allocator and report any bugs you find. >> > Tried it, and it seems to break quite a big chunk of our tests on SPU :)

The greedy allocator is global, but so was the old linear scan allocator. Cameron On Sep 26, 2011, at 2:12 AM, Carlo Alberto Ferraris <cafxx at strayorange.com> wrote: > Just a quick question: is greedy still a local allocator (i.e. only takes into consideration the current bb) or a global one (takes into consideration the whole function)? > <cafxx.vcf> >

On Sep 26, 2011, at 2:41 AM, 陳韋任 wrote: >> The greedy allocator is global, but so was the old linear scan allocator. > > In http://blog.llvm.org/2011/09/greedy-register-allocation-in-llvm-30.html > , it says "The algorithm is local, and it cannot clean up messes that > extend beyond a single basic block". Does it mean the rewriter algorithm > not the linear scan?

Il 26/09/2011 16:49, Jakob Stoklund Olesen ha scritto: > On Sep 26, 2011, at 2:41 AM, 陳韋任 wrote: > >>> The greedy allocator is global, but so was the old linear scan allocator. >> In http://blog.llvm.org/2011/09/greedy-register-allocation-in-llvm-30.html >> , it says "The algorithm is local, and it cannot clean up messes that >> extend beyond a single basic

> The greedy allocator is global, but so was the old linear scan allocator. In http://blog.llvm.org/2011/09/greedy-register-allocation-in-llvm-30.html , it says "The algorithm is local, and it cannot clean up messes that extend beyond a single basic block". Does it mean the rewriter algorithm not the linear scan? Regards, chenwj -- Wei-Ren Chen (陳韋任) Computer Systems Lab,

> On Sep 26, 2017, at 2:39 PM, Geoff Berry via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi all, > > Mikael reported a machine verification failure in his out-of-tree target with the MachineCopyPropagation changes to forward registers (which is currently reverted). The verification in question is: > > *** Bad machine code: Multiple connected components in live

> On Sep 26, 2017, at 3:33 PM, Geoff Berry <gberry at codeaurora.org> wrote: > > > > On 9/26/2017 6:11 PM, Matthias Braun wrote: >>> On Sep 26, 2017, at 2:39 PM, Geoff Berry via llvm-dev <llvm-dev at lists.llvm.org> wrote: >>> >>> Hi all, >>> >>> Mikael reported a machine verification failure in his out-of-tree target

It seems like it might be a legitimate complaint from the register allocator. It's trying to get an accumulator (not a general purpose register) and the accumulator is 64 bit. It's using a part of the Mips backend that I have not worked in so I have to research this a bit. The multiply instruction is a pseudo multiply in the mips backend and it needs the accumulator which a special

Hi all, Mikael reported a machine verification failure in his out-of-tree target with the MachineCopyPropagation changes to forward registers (which is currently reverted). The verification in question is: *** Bad machine code: Multiple connected components in live interval *** - function: utils_la_suite_matmul_ref - interval: %vreg77

> On Sep 26, 2017, at 8:24 PM, Geoff Berry via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > On 9/26/2017 6:47 PM, Matthias Braun wrote: >>> On Sep 26, 2017, at 3:33 PM, Geoff Berry <gberry at codeaurora.org <mailto:gberry at codeaurora.org> <mailto:gberry at codeaurora.org <mailto:gberry at codeaurora.org>>> wrote: >>> >>>

On 9/26/2017 6:11 PM, Matthias Braun wrote: > >> On Sep 26, 2017, at 2:39 PM, Geoff Berry via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> Hi all, >> >> Mikael reported a machine verification failure in his out-of-tree target with the MachineCopyPropagation changes to forward registers (which is currently reverted). The verification in question is: