similar to: [LLVMdev] Instruction Scheduling - migration from v3.1 to v3.2

I am migrating the llvm/clang derived compiler for our processor from the v3.1 to v3.2 codebase. This has mostly gone well except that instruction latency scheduling is no longer happening. The people who implemented this previously sub-classed 'ScheduleDAGInstrs' and implemented the virtual methods 'computeLatency' and 'computeOperandLatency'. However, these methods

I'm unclear how does DFAPacketizer and the scheduler know a given instruction is a load. Here is what I'm talking about Let's assume my VLIW target is described as follows: def MyTargetItineraries : ProcessorItineraries<[Slot0, Slot1], [], [ .............................. InstrItinData<RI, [InstrStage<1, [Slot0, Slot1]>]>,

Hi everyone, The MachineLICM pass has a heuristic such that, even in low-register-pressure situations, it will refuse to hoist "cheap" instructions out of loops. By default, when an itinerary is available, this means that all of the defined operands are available in at most 1 cycle. ARM overrides this, and provides this more-customized definition: bool ARMBaseInstrInfo::

> In particular, the LoadLatency is used in defaultDefLatency: > > /// Return the default expected latency for a def based on it's opcode. > unsigned TargetInstrInfo::defaultDefLatency( > const MCSchedModel &SchedModel, const MachineInstr *DefMI) const { > if (DefMI->isTransient()) > return 0; > if (DefMI->mayLoad()) > return

> On Mar 5, 2018, at 6:28 PM, Matthias Braun <mbraun at apple.com> wrote: > > > >> On Mar 5, 2018, at 6:14 PM, Andrew Trick via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> >> >>> On Mar 5, 2018, at 3:38 PM, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at

> On Mar 5, 2018, at 6:14 PM, Andrew Trick via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > >> On Mar 5, 2018, at 3:38 PM, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: >> >> When Ahmed and I worked on the decompiler, we first targeted MC. Going to MI was more difficult and really wouldn’t have gotten us a

hi all, I installed v3.2 from source and now dom0 is booting well. But when I tried to start domU it shows the following error message and seems hanging. EXT3-fs: mounted filesystem with ordered data mode. EXT3-fs warning: mounting unchecked fs, running e2fsck is recommended EXT3 FS on hda1, internal journal device-mapper: ioctl: 4.7.0-ioctl (2006-06-24) initialised: dm-devel@redhat.com

On Tue, Mar 6, 2018 at 5:55 AM, Andrew Trick via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > > On Mar 5, 2018, at 6:28 PM, Matthias Braun <mbraun at apple.com> wrote: > > > > On Mar 5, 2018, at 6:14 PM, Andrew Trick via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > On Mar 5, 2018, at 3:38 PM, Quentin Colombet <qcolombet at

On Jul 22, 2013, at 11:50 AM, Tom Stellard <tom at stellard.net> wrote: > Hi, > > I'm working on defining a SchedMachineModel for the Southern Islands > family of GPUs, and I have two questions related to the > MachineScheduler. > > 1. I have a resource that can process 15 instructions at the same time. > In the TableGen definitions, should I do: > > def

> On Mar 5, 2018, at 3:38 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > When Ahmed and I worked on the decompiler, we first targeted MC. Going to MI was more difficult and really wouldn’t have gotten us a lot of benefits. Instead, Ahmed pushed for directly decompiling to IR (look for dagger). Thanks for the pointer Quentin. > I would actually be in favor for more

I am stuck trying to adapt my out-of-target implementation to build on SVN head (actually the v3.8 branch, rev #257626). This is currently working on the v3.7.1 sources, but the changes to 'llvm::ScheduleDAGInstrs' have me stumped as to how to revise my implementation to track the changes to this class. Our 'SHAVEAsmScheduler' derives from 'ScheduleDAGInstrs' and uses

Hi, I am extending LLVM for HPC applications. As one of them, I am trying to make MachinePipeliner available on AArch64 + Scalable Vector Extension environment. MachinePipeliner is currently used only by Hexagon CPU. Since it is a very portable implementation, I think that it will actually work just by adding a little code for many CPUs(See Code [2]). The current MachinePipeliner is written on

Hi, I'm working on defining a SchedMachineModel for the Southern Islands family of GPUs, and I have two questions related to the MachineScheduler. 1. I have a resource that can process 15 instructions at the same time. In the TableGen definitions, should I do: def HWVMEM : ProcResource<15>; or let BufferSize = 15 in { def HWVMEM : ProcResource<1>; } 2. Southern Islands has

> On Mar 6, 2018, at 4:20 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> wrote: > > To be clear then, resolveSchedClass should be moved from TargetSchedModel into MCSchedModel (which is where I originally wanted it). Any TargetInstrInfo APIs called from SchedPredicate should be moved to MCInstrInfo, which should be straightforward but annoying. > > Personally, I

Hello, Please consider including upstream commit 08e34eb14fe4cfd934b5c169a7682a969457c4ea in the next v3.2.y release. It was included upstream as of v3.3-rc1. It has been tested and confirmed to resolve http://bugs.launchpad.net/bugs/1154608 . commit 08e34eb14fe4cfd934b5c169a7682a969457c4ea Author: Laszlo Ersek <lersek at redhat.com> Date: Sun Dec 11 01:48:59 2011 +0000

Hello, Please consider including upstream commit 08e34eb14fe4cfd934b5c169a7682a969457c4ea in the next v3.2.y release. It was included upstream as of v3.3-rc1. It has been tested and confirmed to resolve http://bugs.launchpad.net/bugs/1154608 . commit 08e34eb14fe4cfd934b5c169a7682a969457c4ea Author: Laszlo Ersek <lersek at redhat.com> Date: Sun Dec 11 01:48:59 2011 +0000

On Tue, Nov 17, 2015 at 11:15 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 11/17/2015 12:26 PM, Rail Shafigulin wrote: > >> >> I tried setting >> let mayLoad = 1 { >> class InstrLD .... { >> } >> } >> >> But that didn't seem to work. When I looked at the debug output the >> latency for the load

Here are the results of me playing around with the new EXPERIMENTAL release v3.1 of clang for Windows using MinGW32: 0. You don't need to go through the nightmare of building clang v3.1 yourself - it is right there on the download page, albeit at the very bottom. 1. Install MinGW32 in the directory C:\MinGW and nowhere else. Otherwise you'll get all sorts of errors about missing

I recently tried to update my Aastra 57i to version 3.2 and ran into a problem. It won't properly register and says "contact mismatch". I added "sip contact matching: 2" to aastra.cfg, but that didn't help. When I look at the SIP trace, but I see is the Aastra sending a REGISTER and Asterisk replying with the 401. The phone then sends the REGISTER again, this time

In data venerdì 26 giugno 2015 17:35:35, Chen Hanxiao ha scritto: > - Btrfs-progs v4.1 introduced new feature of changing > uuid of btrfs partition. > This patch add support of this. > > - Introduce set_uuid_random > > - uuids.c did a lot of deplicated work for changing uuid > of fs. Use existing functions. > > v3.1: fix typos > v3: set errno if feature is