similar to: [LLVMdev] minimum function ir

On 04/20/2013 02:04 PM, Reed Kotler wrote: > On 04/20/2013 01:30 PM, reed kotler wrote: >> Can I create a "naked" function that has only inline assembler and no >> return IR for example? >> >> If I create just a function will an empty basic block, it's core dumps. >> >> I'm debugging it now. > > Seems that you have to have at least a

On 04/20/2013 01:30 PM, reed kotler wrote: > Can I create a "naked" function that has only inline assembler and no > return IR for example? > > If I create just a function will an empty basic block, it's core dumps. > > I'm debugging it now. Seems that you have to have at least a return instruction. Is that a bug? Why can't I do the return myself if

Hello Reed, Basic blocks need to end with a terminator instruction. There is an "unreachable" terminator instruction, whose documentation says: "the presence of this instruction indicates some higher level knowledge that the end of the block cannot be reached." (see include/llvm/IR/Instructions.h). I've been able to suppress the return using this. I'm not completely

On 01/09/2013 02:44 PM, Eli Friedman wrote: > On Wed, Jan 9, 2013 at 2:19 PM, reed kotler <rkotler at mips.com> wrote: >> On 01/09/2013 01:19 PM, Sean Silva wrote: >>> On Wed, Jan 9, 2013 at 4:14 PM, reed kotler <rkotler at mips.com> wrote: >>>> Does anyone know offhand where this gets added to clang and where the >>>> hook >>>> for

On 01/09/2013 01:19 PM, Sean Silva wrote: > On Wed, Jan 9, 2013 at 4:14 PM, reed kotler <rkotler at mips.com> wrote: >> Does anyone know offhand where this gets added to clang and where the hook >> for processing >> in llc is? >> >> I think that this code has changed recently. > There's

On Mon, Apr 22, 2013 at 8:09 AM, Pete Couperus <pjcoup at gmail.com> wrote: > Hello Reed, > > Basic blocks need to end with a terminator instruction. > There is an "unreachable" terminator instruction, whose documentation says: > "the presence of this instruction indicates some higher level knowledge > that the end of the block cannot be reached." >

On Wed, Jan 9, 2013 at 2:19 PM, reed kotler <rkotler at mips.com> wrote: > On 01/09/2013 01:19 PM, Sean Silva wrote: >> >> On Wed, Jan 9, 2013 at 4:14 PM, reed kotler <rkotler at mips.com> wrote: >>> >>> Does anyone know offhand where this gets added to clang and where the >>> hook >>> for processing >>> in llc is?

I understand that but falling back makes the compilation slower. I'm wondering what could be done to remove this restriction about fast-isel not being able to handle non legal types. ________________________________________ From: Anton Korobeynikov [anton at korobeynikov.info] Sent: Sunday, August 31, 2014 12:55 AM To: Reed Kotler Cc: LLVMdev at cs.uiuc.edu Subject: Re: [LLVMdev] lowering

On 10/15/2013 01:30 PM, Rafael Espíndola wrote: > On 14 October 2013 21:56, reed kotler <rkotler at mips.com> wrote: >> I would like to do constant pools over an entire module instead of just on a >> per function basis as constant islands does it now. >> >> It seems there are two options for this: >> >> 1) collect the machine functions with their

On Feb 17, 2013, at 1:01 PM, Reed Kotler <rkotler at mips.com> wrote: > On 02/17/2013 12:48 PM, Andrew Trick wrote: >> On Feb 16, 2013, at 1:31 PM, Cameron Zwarich <zwarich at apple.com> wrote: >> >>> That's exactly the right place. >> Really? You don't want the expansion to be optimized? You want to specify a machine model for the pseudo's

The problem is that everything about the mips32 and micro mips 16 instruction is the same, aside from the encoding in to binary. Seems like maybe we need to extend the notion of an instruction so that it can have alternate encodings depending on subtarget. On 09/05/2012 08:28 PM, Jim Grosbach wrote: > The instructions are defined by their encodings, not the assembly syntax. You want

On 10/15/2013 01:39 PM, reed kotler wrote: > On 10/15/2013 01:30 PM, Rafael Espíndola wrote: >> On 14 October 2013 21:56, reed kotler <rkotler at mips.com> wrote: >>> I would like to do constant pools over an entire module instead of >>> just on a >>> per function basis as constant islands does it now. >>> >>> It seems there are two

On 02/17/2013 01:08 PM, Andrew Trick wrote: > > On Feb 17, 2013, at 1:01 PM, Reed Kotler <rkotler at mips.com > <mailto:rkotler at mips.com>> wrote: > >> On 02/17/2013 12:48 PM, Andrew Trick wrote: >>> On Feb 16, 2013, at 1:31 PM, Cameron Zwarich<zwarich at apple.com> wrote: >>> >>>> That's exactly the right place.

Fast-isel is not equipped in general to deal with non legal types. It would seem that an llvm assembler pass run after clang but before llvm could do the lowering though. Any thoughts? Reed

In that case it tries to do something but fails. rkotler at ubuntu-rkotler:~/testmips16$ /home/rkotler/llvmw/install/bin/bugpoint casts.bc -llc-safe --safe-tool-args -target=mips-linux-gnu -mcpu=mips16 -mips16-constant-islands Read input file : 'casts.bc' *** All input ok Initializing execution environment: Found llc: /home/rkotler/llvmw/install/bin/llc Running the code

Right now inline assembler just passes through to the assembler if there is no direct object emitter. If there is a direct object emitter, it gets processed in Asm parser and MC instructions are produced. I propose that the initial parsing happen very early and the inline assembly code be replaced with a sequence of MachineInstructions in the basic block where it occurs. Then code like

The micro mips processor assembly language is basically 100% the same as mips32/mips64. There are some assembler directives you add but for a base port, but that is all you need to do. However, the binary instruction encoding is entirely different. There are a combination of 16 and 32 bit instruction encodings. The question is, what's the best way to handle this? Extending tablegen ?

----- Original Message ----- > From: "Reed Kotler" <rkotler at mips.com> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: LLVMdev at cs.uiuc.edu > Sent: Friday, November 22, 2013 11:18:53 PM > Subject: Re: bugpoint question > > In that case it tries to do something but fails. > > rkotler at ubuntu-rkotler:~/testmips16$ >

Yes, you could have mips16 and fastcc. Mips16 just means that processor mode to execute that function is "mips16". So in a mips16 designated function, I will just emit mips16 instructions and in a "nomips16" function, just emit normal mips32 instructions. I tend to call this "mips32" normal mode, "standard encoding" because in reality the processor is

My understanding was that micro mips was similar to Thumb2, in that the smaller encodings have constraints on which registers can be read/written, because of the narrowing of the register fields in the encoding. If that's the case, then it definitely makes sense to model the micro mips instruction set as distinct from the mips32 instruction set, in basically the same way that Thumb2 is done.