similar to: [LLVMdev] Is r174746 broken on ARM?

----- Original Message ----- > From: "Dmitry Antipov" <antipov at dev.rtsoft.ru> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: "Renato Golin" <renato.golin at linaro.org>, llvmdev at cs.uiuc.edu > Sent: Thursday, April 4, 2013 3:22:05 AM > Subject: Is r174746 broken on ARM? > > Hello Hal, > > I have a strong suspicion

On 04/04/2013 05:09 PM, Hal Finkel wrote: > Looking briefly at the code in comment 5 of PR15581, is that the pre-decrement case? > I can't test that case on PPC, so I can certainly believe that there is a problem somewhere. > The relevant code is a little farther down: > > APInt OV = > cast<ConstantSDNode>(Offset)->getAPIntValue(); > if (AM ==

On 04/10/2013 10:22 PM, Hal Finkel wrote: >> Okay, great! Can you please generate a test case? In case you don't >> know, an easy way is this: place an assert that will crash the code >> generation in the pre-dec case you've highlighted, then use bugpoint >> to produce a reduced test case for the crash. > > [list not cc'd] > > Were you able to make

Dear list, I have to read a not-so-small bunch of not-so-small Excel files, which seem to have traversed Window 3.1, Windows95 and Windows NT versions of the thing (with maybe a Mac or two thrown in for good measure...). The problem is that 1) I need to read strings, and 2) those strings may have various encodings. In the same sheet of the same file, some cells may be latin1, some

Bill Wendling wrote: > On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote: > >> Bill Wendling wrote: >>> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: >>> >>>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >>>> >>>>> Our architecture has 1-bit boolean predicate registers. >>>>> >>>>> I've

Bill Wendling wrote: > On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > >> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >> >>> Our architecture has 1-bit boolean predicate registers. >>> >>> I've defined comparison >>> >>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set

On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote: > Bill Wendling wrote: >> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: >> >>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >>> >>>> Our architecture has 1-bit boolean predicate registers. >>>> >>>> I've defined comparison >>>> >>>> def

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I'm relatively new to LLVM so apologies in advance if this is a dumb question. I've been experimenting with re-targeting LLVM onto a 16-bit micro which has pre and post increment and decrement addressing modes. I've been using llvm-gcc to generate llvm bitcode and llvm 2.7 to go from here to my target assembly code. I've got the Combine pass to deal with

Hello, it looks like I do have infinite loop in llc on linux/armv7 platform somewhere in llvm::SmallVectorImpl. Two backtraces obtained with 10 seconds delay are: 0x0099be14 in llvm::SmallVectorTemplateCommon<llvm::SDNode*>::setEnd (this=0x7ee90b38, P=0x5c06988) at /export/home/karel/vcs/llvm-head/include/llvm/ADT/SmallVector.h:103 103 void setEnd(T *P) { this->EndX = P; }

Hi, >> DAGCombiner::visitBRCOND() has code: >> >> SDValue N1 = N->getOperand(1); >> SDValue N2 = N->getOperand(2); >> >> ... >> >> SDNode *Trunc = 0; >> if (N1.getOpcode() == ISD::TRUNCATE&& N1.hasOneUse()) { >> // Look past truncate. >> Trunc = N1.getNode(); >> N1 = N1.getOperand(0);

Previously we placed large files in g#get_cachedir () (usually /var/tmp). However the problem is this ties the libguestfs appliance and the virt-v2v overlay files to the same location. When virt-v2v is run in a container, or any other situation where local storage is limited, it's helpful to be able to put the overlay files on an externally mounted PVC, which might be using NFS and shared

I've looked at the ExceptionDemo and the SysV AMD64 ABI and I'm unclear on who, and when, the 'exception_cleanup' function is called. I have some working exceptions but my cleanup routine is never called. In the ExceptionDemo I turned on debug output and saw that the delete function is also not called. -- edA-qa mort-ora-y -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --

Hello all, can someone do a quick review of the one-line proposal fix attached to http://llvm.org/bugs/show_bug.cgi?id=15581? I'm not sure that I can explain why it works, but it (hopefully) is, so I really need a feedback with this. Thanks, Dmitry

Hello, I made an interesting observation related to the "Clocksource tsc unstable (delta = -2999660320319 ns)" problem. In the log of ntpd I found: Oct 5 03:46:35 greenville-dom0 ntpd[4020]: kernel time sync status change 6001 Oct 5 04:03:41 greenville-dom0 ntpd[4020]: kernel time sync status change 2001 Oct 5 05:29:03 greenville-dom0 ntpd[4020]: kernel time sync status change

Hello, I will be very obliged if someone can help me with this statistical R problem: I am trying to do a Pearson correlation on my datasets X, Y with randomization test. My X and Y datasets are pairs. 1. I want to randomize (rearrange) only my X dataset per row ,while keeping the my Y dataset as it is. 2. Then Calculate the correlation for this pair, and compare it to your true

On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > >> Our architecture has 1-bit boolean predicate registers. >> >> I've defined comparison >> >> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;