similar to: [LLVMdev] r176991 - Really fix the MIPS test.

Displaying 20 results from an estimated 4000 matches similar to: "[LLVMdev] r176991 - Really fix the MIPS test."

2013 Jan 11
0
[LLVMdev] adding IR attributes to llvm
I think that Bill Wendlings new attribute implementation would allow me to do this but it is not ready yet. Maybe it's okay to just add them to the list of function attributes as I suggested. But in the end, someone has to approve the checkin. On 01/11/2013 07:35 AM, Reed Kotler wrote: > Yes, you could have mips16 and fastcc. > > Mips16 just means that processor mode to execute
2013 Jan 11
2
[LLVMdev] adding IR attributes to llvm
Yes, you could have mips16 and fastcc. Mips16 just means that processor mode to execute that function is "mips16". So in a mips16 designated function, I will just emit mips16 instructions and in a "nomips16" function, just emit normal mips32 instructions. I tend to call this "mips32" normal mode, "standard encoding" because in reality the processor is
2013 Mar 28
3
[LLVMdev] proposed change to class BasicTTI and dual mode mips16/32 working
So I have dual mode 16/32 compilation on a per function basis working. I need to clean up some things and then will push the change. I managed to do everything without needing to change anything in target independent code thus far. It was a fun puzzle to solve as to how to do this using only the given APIs. As for the BasicTransformInfoPassass, for this dual mode I'm using
2013 Jan 09
2
[LLVMdev] attributes
I need to add two function attributes to clang that I can subsequently process in llvm. void __attribute__((mips16)) foo16 (); void __attribute__((nomips16)) foo32 (); int main() { foo16(); foo32(); } Does anyone know offhand where this gets added to clang and where the hook for processing in llc is? I think that this code has changed recently. These options mimick those of gcc.
2012 May 14
0
[LLVMdev] getMinimalPhysRegClass
On May 14, 2012, at 2:28 PM, reed kotler wrote: > I'm not using getMinimalPhysRegClass. Some target independent code is using it. Probably PEI. > It makes trouble for us and I would like to submit a patch to make it a virtual function so that I can override it and make it meaningful for Mips, as long as this method still exists. > > I want to add another register class for
2013 Jan 11
0
[LLVMdev] adding IR attributes to llvm
Depends on whether its actually the calling convention, or just an annotation (I don't know MIPS that well). Could you ever have a case where you want to declare a function as both mips16 and fastcc, or some other explicit calling convention? For PTX, we added two calling conventions to mark kernel functions (callable by host) from device functions (not callable by host). But this
2013 Mar 14
0
[LLVMdev] initial putback for implementing mips16/nomips16 attributes - please review
I added one method which clears the list of register classes. Then there is a change to mips16 code which simulates switching from mips32 to mips16 mode in the same module. It seems to work fine in that I can run this version of llvm for mips16 and it works identical to the one without this code. Beyond the "make check" I have run test-suite against this version. We could just
2012 May 14
4
[LLVMdev] getMinimalPhysRegClass
On 05/14/2012 02:17 PM, Jakob Stoklund Olesen wrote: > On May 14, 2012, at 1:02 PM, reed kotler wrote: > >> Does anyone understand the purpose of : >> >> TargetRegisterInfo::getMinimalPhysRegClass ??? > Barely. > >> Why is there the presumption to use the minimal subclass? > The function can be traced back to a time when men were men and registers belonged to
2012 May 14
0
[LLVMdev] getMinimalPhysRegClass
Reed, On May 14, 2012, at 3:45 PM, reed kotler <rkotler at mips.com> wrote: > On 05/14/2012 02:42 PM, Jakob Stoklund Olesen wrote: >> On May 14, 2012, at 2:28 PM, reed kotler wrote: >> >>> I'm not using getMinimalPhysRegClass. Some target independent code is using it. >> Probably PEI. >> >>> It makes trouble for us and I would like to
2012 May 14
3
[LLVMdev] getMinimalPhysRegClass
On 05/14/2012 02:42 PM, Jakob Stoklund Olesen wrote: > On May 14, 2012, at 2:28 PM, reed kotler wrote: > >> I'm not using getMinimalPhysRegClass. Some target independent code is using it. > Probably PEI. > >> It makes trouble for us and I would like to submit a patch to make it a virtual function so that I can override it and make it meaningful for Mips, as long as this
2013 Jan 11
2
[LLVMdev] adding IR attributes to llvm
For target dependent function level attributes, do I need to actually add them to the enumeration in attributes.h? I have for example, mips16 and nomips16 as attributes. Or is this supposed to be done with cc <n>
2013 Apr 25
1
[LLVMdev] issues with InlineAsm class and #APP/#NOAPP
I'm happy to send you my patch as it stands today. It's not cleaned up yet all or tested thoroughtly but you can look at what I'm doing and maybe suggest some alternate paths and if it's not a matter of redoing everything, I would consider making some changes. Here is a sample stub: Consider this line of code: extern float fpff(float); We have no idea if this is a mips16 or
2013 Apr 19
0
[LLVMdev] funny llvm bug
This came about in trying to implement some stubs used by gcc mips16 for allowing floating point interoperability with mips32. You get the following looking code from gcc -mips16: # Stub function for foovf (float) .section .mips16.fn.foovf,"ax", at progbits .align 2 .set nomips16 .set nomicromips .ent __fn_stub_foovf .type __fn_stub_foovf, @function __fn_stub_foovf: la
2013 Apr 01
0
[LLVMdev] proposed change to class BasicTTI and dual mode mips16/32 working
On 04/01/2013 12:31 PM, Chandler Carruth wrote: > On Thu, Mar 28, 2013 at 12:22 PM, Nadav Rotem <nrotem at apple.com > <mailto:nrotem at apple.com>> wrote: > > IMHO the right way to handle target function attributes is to > re-initialize the target machine and TTI for every function (if > the attributes changed). Do you have another solution in mind ?
2013 Mar 28
1
[LLVMdev] proposed change to class BasicTTI and dual mode mips16/32 working
On 03/28/2013 12:22 PM, Nadav Rotem wrote: > Hi Reed, > > On Mar 28, 2013, at 12:18 PM, Reed Kotler <rkotler at mips.com > <mailto:rkotler at mips.com>> wrote: > >> As for the BasicTransformInfoPassass, for this dual mode I'm using >> createNoTargetTransformInfoPass right now. > > So, MIPS does not need LSR, LowerSwitch and other optimizations
2014 Feb 04
2
[LLVMdev] emitting function stub for mips16 floating point patch
On 02/04/2014 09:49 AM, Rafael EspĂ­ndola wrote: > On 4 February 2014 12:37, reed kotler <rkotler at mips.com> wrote: >> How is alignment set? > Of a symbol? EmitValueToAlignment. > > A tip on how to find this is to look at what clang prints > (".align...") and grep for it "git grep '\.align'"). > > Cheers, > Rafael Not on a symbol but
2014 Jan 31
5
[LLVMdev] emitting function stub for mips16 floating point patch
I'm rewriting this patch for the stubs to not use outputing of raw text. Generating the instructions is very straightforward and that part is done. I'm translating the actual function now. How do you emit an .ent or .globl from asm printer? .type ? .end ?? .section ??? I'm studying the classes now but it should be simple to do so if you know, you can save me some time because this
2013 Mar 22
0
[LLVMdev] proposed change to class BasicTTI
Hi Reed, We will need to reconstruct the target machine and the TTI chain when the function attributes change. We currently don't have code for doing that but I suggest that you talk with Bill Wendling about the best way to implement this. Thanks, Nadav On Mar 22, 2013, at 11:30 AM, Reed Kotler <rkotler at mips.com> wrote: > Just realized that BasicTransformInfoClass is an
2012 Jan 20
0
[LLVMdev] various mips16 and micro mips issues
On Fri, Jan 20, 2012 at 1:59 PM, reed kotler <rkotler at mips.com> wrote: > We are starting to look at the mips16 and micro mips ports. > > There are various design issues that people may have some good input on. > Especially in how to structure the TD files and other optimizer issues. > > Mips16 is sort of like thumb and Micro Mips like thumb2 as far as I > understand.
2013 Apr 17
1
[LLVMdev] interesting IR problem related to mips 16
When a mips16 wants to return a floating point value, it's at a quandary in mixed mode programs (having both mips16 and mips32 code). float foo() { return 1.0; } Mips16 code is compiled in soft float, with there being an options to have the emulation library be written in mips32 and use floating point instructions in those mips32 support functions (if the machine supports floating