similar to: [LLVMdev] AESOP autoparallelizing compiler

On 03/03/2013 02:09 PM, Timothy Mattausch Creech wrote: > Hi, > We would like to inform the community that we're releasing a version of our research compiler, "AESOP", developed at UMD using LLVM. AESOP is a distance-vector-based autoparallelizing compiler for shared-memory machines. The source code and some further information is available at > >

Hi Sebastian, Sure! The bulk of LMDA was written by Aparna Kotha (CCd). It computes dependences between all instructions, computes the resulting direction vectors in the function, then associates them all with loops. At a high level, the dependence analysis consults with AliasAnalysis, and ScalarEvolution before resorting to attempting to understand the effective affine expressions and

----- Original Message ----- > From: "Timothy Mattausch Creech" <tcreech at umd.edu> > To: "Sebastian Dreßler" <dressler at zib.de> > Cc: "Aparna Kotha" <akotha at umd.edu>, llvmdev at cs.uiuc.edu > Sent: Sunday, March 3, 2013 11:32:49 AM > Subject: Re: [LLVMdev] AESOP autoparallelizing compiler > > Hi Sebastian, > Sure!

Hi, On 03/03/2013 07:09 AM, Timothy Mattausch Creech wrote: > [...] > The main components of the released implementation are loop memory > dependence analysis and parallel code generation using calls to POSIX > threads. The loop memory dependence analysis sounds very interesting to me. Could you provide some more information regarding its capabilities? Cheers, Sebastian -- Mit

Hi Rahul, Thanks for your interest! Our work does not attempt to make any significant contributions to alias analysis, and acts as a client to existing LLVM AA. Furthermore, the options passed to the AESOP frontend scripts are obeyed at compile time, but at link time certain transformations occur unconditionally. Here, AESOP has actually thwarted your experiment by performing inlining just

On Mon, Mar 04, 2013 at 03:01:15PM +0800, 陳韋任 (Wei-Ren Chen) wrote: > Hi Timothy, > > > We would like to inform the community that we're releasing a version of our research compiler, "AESOP", developed at UMD using LLVM. AESOP is a distance-vector-based autoparallelizing compiler for shared-memory machines. The source code and some further information is available at

Hi Timothy, Today I happened to download the code and do some experiments. I actually wanted to see how you handle inter-procedure alias analysis. So, I set inline threshold to zero and tried out following example =============================================== #define N 1024 void func(double *A, double *B) { int i; for (i=1; i<N-2; i++) { B[i] = A[i] + i*3; } } void func1(double

Hi Timothy, > We would like to inform the community that we're releasing a version of our research compiler, "AESOP", developed at UMD using LLVM. AESOP is a distance-vector-based autoparallelizing compiler for shared-memory machines. The source code and some further information is available at > > http://aesop.ece.umd.edu > > The main components of the released

Hi Preston, Thank you for the prompt response. You can use DependenceAnalysis to get the info you want by expensively > testing all pairs of memory references. Isn't all pairs testing incorrect in the sense that a pair may only exist for a certain path? Consider the following example. A[i] = 42; // S1 if( condition ) // C1 { A[i] = 20; // S2 } B[i] = A[i];

On 03/01/2013 02:57 PM, Hal Finkel wrote: Hi Hal, thanks for feedback. > Jiong, I am happy to see the Tile backend being offered for upstream inclusion. Among other things, in the long run, this may help inform and motivate many-core capabilities in LLVM. > > First, can you elaborate on the future maintenance and development plans for the target code? Do you plan to add SIMD support?

Hi, On behalf of Tilera Corporation, I'd like to contribute llvm ports to Tilera's TILE-Gx architecture and wish this could be submitted to main llvm tree. TILE-Gx is a VLIW architecture with 64-bit registers, 64-bit address space, and 64-bit instructions. TILE-Gx has load-store architecture ISAs. More information on the architectures is available at

On 03/02/2013 04:50 AM, Dmitri Gribenko wrote: > You also need tests for Clang bits, too. > > Mechanical issues: > > +/// getTileRegisterNumbering - Given the enum value for some register, > +/// return the number that it corresponds to. > > Please don't duplicate function and class name in comments. Existing > code does this, but current style guidelines advise not

On Thu, Mar 7, 2013 at 6:33 PM, Jiong Wang <jiwang at tilera.com> wrote: > Hi all, > > Updated the patches for TILE-Gx backend: > > 1. added initial regression tests for tilegx codegen. > 2. added initial regression tests for MC Layer. > 3. fixed those commenting style issues. > > please review, thanks. This is a huge patch, and reviewing it in tar.gz is hard. To

Hi Chris, could you please comment on committing TILE-Gx backend into community? ========== TILE-Gx Status =========== Features Supported === 1. general function. 2. PIC/TLS/JumpTable. 3. Instructoin Bundling for VLIW. 4. Asm Parser 5. MC Layer (aware of instruction bundle), MCJIT support. 6. Initial regression tests for CodeGen & MC Layer. Regression Result === Expected Passes : 13363

----- Original Message ----- > From: "Jiong Wang" <jiwang at tilera.com> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>, cfe-dev at cs.uiuc.edu > Sent: Friday, March 1, 2013 1:34:15 AM > Subject: Re: [LLVMdev] RFC: TileGX, a new backend for Tilera's many core processor >

----- Original Message ----- > From: "Jiong Wang" <jiwang at tilera.com> > To: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>, cfe-dev at cs.uiuc.edu > Sent: Thursday, February 28, 2013 6:09:20 PM > Subject: [LLVMdev] RFC: TileGX, a new backend for Tilera's many core processor > > Hi, > > On behalf of Tilera Corporation,

On Mar 19, 2013, at 8:58 PM, Jiong Wang <jiwang at tilera.com> wrote: > Hi Chris, > > could you please comment on committing TILE-Gx backend into community? Hi Jiong, I don't have any special advice here. It sounds like the general functionality level is high enough. Taking it into mainline sounds great, so long as it is reviewed by someone. -Chris > > >

On 03/08/2013 04:48 AM, Dmitri Gribenko wrote: > On Thu, Mar 7, 2013 at 6:33 PM, Jiong Wang <jiwang at tilera.com> wrote: >> Hi all, >> >> Updated the patches for TILE-Gx backend: >> >> 1. added initial regression tests for tilegx codegen. >> 2. added initial regression tests for MC Layer. >> 3. fixed those commenting style issues. >>

On Fri, Mar 08, 2013 at 12:33:58AM +0800, Jiong Wang wrote: > please review, thanks. configure.ac: I guess it would be preferable to not enable it by default for the moment. include/llvm/Support/FEnv.h: What is supposed to handle? Build on/for Tile? Does the platform provide fenv.h but in a broken way? lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp: Is this change intentional? Personally, I

Hi all, Updated the patches for TILE-Gx backend: 1. added initial regression tests for tilegx codegen. 2. added initial regression tests for MC Layer. 3. fixed those commenting style issues. please review, thanks. I have tried to understand the new backend requirement for LLVM from the mailiing list archive, it's sure TILE-Gx backend will be actively maintained & improved, it's