similar to: [LLVMdev] Calling with register indirect reference instead of memory indirect reference.

Hello > I am wondering if the modification made to the DAG is causing a problem, and > can it be done at all? If I cannot do this, is there any other place I can > look at, to make this work. It's hard to tell w/o seeing the exact code / DAG. Note, however, that this assertion is seen on simple LLVM IR: http://llvm.org/bugs/show_bug.cgi?id=15053 So, it might be not your bug after

Hi Eli, I have tried this, but the resulting tool-chain was broken. There are only two references to "CALL64m": the definition in X86Instr64bit.td, and an entry in X86InstrInfo.cpp. After commenting both out, compilation of a large application fails with: llc: ScheduleDAG.cpp:462: void llvm::ScheduleDAGTopologicalSort::InitDAGTopologicalSorting(): Assertion `Node2Index[SU->NodeNum]

On Tue, Jun 8, 2010 at 4:20 PM, David Meyer <pdox at google.com> wrote: > Hi Eli, > I have tried this, but the resulting tool-chain was broken. > There are only two references to "CALL64m": the definition in > X86Instr64bit.td, and an entry in X86InstrInfo.cpp. > After commenting both out, compilation of a large application fails with: > llc: ScheduleDAG.cpp:462:

After removing CALL64m, the resulting DAG has a cycle that cannot be scheduled. I've attached a PDF of the DAG before instruction selection (-view-isel-dags), and after instruction select (-view-sched-dags). Notice how the flag/chain relationships between MOV64rm and CALL64r make it impossible to schedule. Here's the code being compiled: define ccc void @ArgsFree() nounwind { entry:

Andy, So if it is not a feature. then couple questions: First, I also do not see an easy way to restructure work sets in this case - so let's assume std::map is needed here. Then the way I understand it, there are five objects that cause the indeterminism: std::map<const Value *, SUnit *> AliasMemDefs, NonAliasMemDefs; std::map<const Value *, std::vector<SUnit

Hi, I am attempting to modify LLVM to generate code for an architecture which is nearly identical to X86-64, but with a few minor differences. In particular, "call" must always have a register operand, and cannot have a memory operand. Any ideas on how I can express this rule? Thanks, - David -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Tue, Jun 8, 2010 at 2:05 PM, David Meyer <pdox at google.com> wrote: > Hi, > I am attempting to modify LLVM to generate code for an architecture which is > nearly identical to X86-64, but with a few minor differences. > In particular, "call" must always have a register operand, and cannot have a > memory operand. Any ideas on how I can express this rule? Just get

On Oct 16, 2012, at 1:43 PM, Sergei Larin <slarin at codeaurora.org> wrote: > > Andy, > > This is less of a question but rather a status quo verification… > > We currently have certain indeterminism in MI scheduler DAG construction – it is introduces by the use of std::map/std::set during edge traversal. > Result – a random variation in SUnit edge order

We should check dlm->dlm_state under dlm->spinlock though maybe in this case it doesn't hurt. Signed-off-by: Wengang Wang <wen.gang.wang at oracle.com> --- fs/ocfs2/dlm/dlmdomain.c | 13 ++++++------- 1 files changed, 6 insertions(+), 7 deletions(-) diff --git a/fs/ocfs2/dlm/dlmdomain.c b/fs/ocfs2/dlm/dlmdomain.c index 6b5a492..ab82add 100644 --- a/fs/ocfs2/dlm/dlmdomain.c +++

Hi, Can anyone help me to understand the ScheduleDAGInstrs::buildSchedGraph() method? I find the handling of AliasChain is disturbing since: 1. A new alias chain add deps to all possibly aliasing SUs, and then clears those lists. 2. When AliasChain is present, the addChainDependency() method is called, but the target hook areMemAccessesTriviallyDisjoint() called inside

https://bugs.freedesktop.org/show_bug.cgi?id=61635 Priority: medium Bug ID: 61635 Assignee: nouveau at lists.freedesktop.org Summary: glVertexAttribPointer(id, GL_UNSIGNED_BYTE, GL_FALSE,...) does not work Severity: normal Classification: Unclassified OS: All Reporter: rodrigorivascosta at

I have a question about management tool for asterisk. What tool are you used to use to manage asterisk? I have a system with freePBX and I just want to know if is there any tool that better than that. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.digium.com/pipermail/asterisk-users/attachments/20130228/3c67f3b6/attachment.htm>

We have a test 10gR2 RAC cluster using ocfs2 filesystems for the Clusterware files and the Database files. We need to increase the node slots to accomodate new RAC nodes. Is it true that we will need to umount these filesystems for the upgrade (i.e. Database and Clusterware also)? We are planning to use the following command format to perform the node slot increase: # tunefs.ocfs2 ?N 3

Hi jeff! Any news? On Feb 9, 2013 1:53 AM, "Jeff Fifield" <fifield at mtnhigh.net> wrote: > Hi, > > I just saw this thread. I work on llvm at Xilinx but I do not work on > microblaze. > > I will check to see if there is any interest here at Xilinx to contribute > resources to the maintenance of this backend. > > Thanks, > Jeff > > > > On

Hello again, Sorry -- I think I found the problem somewhere else. I was a bit confused and missed the fact that adjustChainDeps() is called a few lines down and does just what I wanted :-) I would like to instead ask another question: Why is I->isCtrl() used in code like // Iterate over chain dependencies only. for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E =

Andy, This is less of a question but rather a status quo verification. We currently have certain indeterminism in MI scheduler DAG construction - it is introduces by the use of std::map/std::set during edge traversal. Result - a random variation in SUnit edge order (which will remain fixed thereafter). Logically, it is the same DAG, but topologically it is a slightly different one,

Signed-off-by: Christoph Hellwig <hch@lst.de> Index: linux-2.6/fs/ocfs2/cluster/tcp.c =================================================================== --- linux-2.6.orig/fs/ocfs2/cluster/tcp.c 2007-05-06 13:51:17.000000000 +0200 +++ linux-2.6/fs/ocfs2/cluster/tcp.c 2007-05-17 15:00:14.000000000 +0200 @@ -261,14 +261,12 @@ out: static void o2net_complete_nodes_nsw(struct o2net_node

Found 15 patches (out of 162) that appeared relevant to ocfs2 1.4. Please review. Sunil

Commit 86781624 ("x86_emulate: PUSH <mem> must read source operand just once") corrected the operands of those of the operations of opcode extension group 5 that only read memory from SrcMem to DstMem, but failed to also switch the use of "dst" here to "src". Reported-by: Anthony Perard <anthony.perard@citrix.com> Signed-off-by: Jan Beulich

Hi all, I am using package lavaan and have created a structural equation model with two exogenous and seven endogenous variables with the following relationships #specify the model m1 = ' # regressions D ~ ma + hs + b4 + b5 + b15 + b16 ma ~ hs + b4 + b5 + b15 + b16 hs ~ b4 + b5 + b15 + b16 b4 ~ el + la b5 ~ el + la