similar to: [LLVMdev] arm compiler benchmarks

What about benchmarks on other Arm devices? On 02/26/2013 02:52 PM, Jim Grosbach wrote: > Cortex-M0 is a Thumb1 only device. There hasn't been any concerted > effort to tune LLVM's Thumb1 output in quite a long time. Even back then > (2008 or so), the effort was mainly to get it to work acceptably, with > the real performance tuning work being done for Thumb2. I'm not >

Cortex-M0 is a Thumb1 only device. There hasn't been any concerted effort to tune LLVM's Thumb1 output in quite a long time. Even back then (2008 or so), the effort was mainly to get it to work acceptably, with the real performance tuning work being done for Thumb2. I'm not surprised that an embedded market focussed compiler like IAR is better tuned for a chip like that. -Jim On Feb

I've not run any on non-iOS devices, and haven't looked at GCC since v4.2.1 due to licensing issues, so I don't have a good feel for comparative benchmarking. -Jim On Feb 26, 2013, at 4:20 PM, Reed Kotler <rkotler at mips.com> wrote: > What about benchmarks on other Arm devices? > > On 02/26/2013 02:52 PM, Jim Grosbach wrote: >> Cortex-M0 is a Thumb1 only

I gave the following function to IAR compiler (targeting CortexM0) and to clang/LLVM 3.2 (clang -O3 -target thumbv6-eabi -emit-llvm) int calleeSave8(int in[]){ int out=0; int i; for(i=0;i<8;i++){ out ^= in[i] & in[(i+1)%8]; }//expand to out = (in[0]&in[1])^(in[1]&in[2])^(in[2]&in[3])^(in[3]&in[4])^(in[4]&in[5])^(in[5]&in[6])^(in[6]&in[7])^(in[7]&in[0])

Hi, clang -O3 -target thumbv7-eabi -emit-llvm ... llc ... -debug -O3 -code-model=small -march=thumb -mcpu=cortex-m3 ... Does generate slightly better code, but it still computes 7 xor + 7 and. Anyway this should be a target independent optimization isn't it ?? Cheers Sebastien On 2013-02-04 16:46, Bill Wendling wrote: > Have you tried armv7? > > -bw > > On Feb 2,

Have you tried armv7? -bw On Feb 2, 2013, at 3:50 PM, matic at nimp.co.uk wrote: > I gave the following function to IAR compiler (targeting CortexM0) and to clang/LLVM 3.2 (clang -O3 -target thumbv6-eabi -emit-llvm) > > int calleeSave8(int in[]){ > int out=0; > int i; > for(i=0;i<8;i++){ > out ^= in[i] & in[(i+1)%8]; > }//expand to out =

I haven't tried using -Os/z on any ARM device for the last 3 years, and back then, -Os would break many things. People normally care about code size on Cortex-R/M and ARM9 or older, and in there, not many LLVM users. --renato On 27 February 2013 00:38, Jim Grosbach <grosbach at apple.com> wrote: > I've not run any on non-iOS devices, and haven't looked at GCC since >

Hi, I would like to execute a MachineFunctionPass after all other passes which modify the machine code. In other words, if we call llc to generate assembly file, that pass should run right before the "Assembly Printer" pass. Is there any official way to enforce this ? Best regards, Sebastien

In fact, on my shelf is running speex using Raisonance Primer2 DK and IAR STM32-SK DK. But I want to save the power consumption of the device runnig speex, and EFM32 seems to be a very good candidate. Also, do yo think that the STM32F103 (Cortex M3 90 MIPS) could be used to run Speex at 4 Kbps in real time? Regards, Nicolas 2010/3/3 Jean-Marc Valin <jean-marc.valin at usherbrooke.ca> >

Hi Everyone, As you may recall (I posted a while back) I'm currently doing a project measuring the energy consumption for different compiler flags. I've now gathered a set of benchmarks which I think are appropriate, for these (very) low end embedded platforms. The benchmarks that have been chosen: - CRC32, SHA - Prime sifting - Integer / floating point matrix multiplication - Cubic

On Jul 31, 2012, at 4:43 AM, James Pallister <james.pallister at embecosm.com> wrote: > Hi Everyone, > > As you may recall (I posted a while back) I'm currently doing a project > measuring the energy consumption for different compiler flags. I've now > gathered a set of benchmarks which I think are appropriate, for these > (very) low end embedded platforms. >

The question is, what should C and C++ compilers do with this code? volatile int x; void foo (void) { x; } This question is not totally stupid: embedded systems use code like this when reading a hardware register has a useful side effect (usually clearing the register). It is reasonably clear that a C compiler should load from x and throw away the value. clang and llvm-gcc do

Hi there. I'm having a problem letting a Samba server (MYSAMBA) authenticate users (using "security = domain" and a "password server = MYPDC") against a Windows 2000 PDC (MYPDC). The Windows 2000 machine seems (I'm not 100% sure about this) to be configured to restrict anonymous and it seems to me that this is where the problem lies but don't know what to do. I

Hi, I am confused about the call to isPhyRegUsed in calculateCalleeSavedRegisters: if (Fn.getRegInfo().isPhysRegUsed(Reg)) { // If the reg is modified, save it! CSI.push_back(CalleeSavedInfo(Reg)); } It seems that isPhyRegUsed returns true if the register is read or written in the function. If this is right, why do we save a register if it is only read in the function ?? I would have

Hai, This is amar. I have a situation like installing IAR compiler on Fedora 8 so i installed compiler with the help of wine 1.2. It successfully installed :) but i got a problem during build the programs it is asking the Dongle key(USB) Drivers.This Dongle key is Licensed key provided by IAR vendor. These Drivers are not installed during Installation process. so I add USB patch to wine1.2

Thanks ! On this forum is also shown this information : http://lists.xiph.org/pipermail/speex-dev/2009-January/007050.html According to vk's results, it could be possible to run Speex at 4/6 & 8 kbps on a Cortex M-3 at 36 MHz ... so not excluding the EFM32 ... Nico 2010/3/3 Pietro Maggi <studiomaggi at gmail.com> > On ST forums there is someone that states it has done an

Hi Eli, Thanks for your response. Actually, I look a lot at the ARM and THUMB1 backend implementations, and this certainly help. My architecture also have specific instructions for SP-relative accesses in a similar way than the Thumb1. During frame lowering, specific machine instructions are emitted so there’s no issue there. Also during ISelDagToDag I am able to select the right instructions.

In MyTargetRegisterInfo.td file, I defined separated register classes for general purpose registers and for the SP register: def GR16 : RegisterClass<"CPU74", [i16], 16, (add R0, R1, R2, R3, R4, R5, R6, R7)>; def SSP : RegisterClass<"CPU74", [i16], 16, (add SP)>; The SP can not be used in general purpose arithmetic instructions, therefore I defined the following

Hello, as a newbee, I'd appreciate some support on regression test setup. Specifically, I am interrested in the feature of tail call optimizations for the ARM v6m targets. This feature currently seems to be completely deactivated at the moment (v6m being based on thumb1 ?!). According to my code-reading, this feature will involve some modifications in epilogue generation. My work on a gcc

Yes, it's a bug. Please review https://reviews.llvm.org/D31716 On 4/5/2017 3:50 AM, Renato Golin wrote: > On 21 March 2017 at 18:32, Peter Jakubek via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> I think the current implementation for the call "bl __aeabi_idiv0" in >> builtins\arm\udivsi3.S is broken. >> At least for the case that __aeabi_idiv0