similar to: [LLVMdev] Need the X86 Application Binary Interface(ABI) Documentation

Shashidhar, Here's it for 32 and 64 bits. https://developer.apple.com/library/mac/#documentation/DeveloperTools/Conceptual/LowLevelABI/130-IA-32_Function_Calling_Conventions/IA32.html#//apple_ref/doc/uid/TP40002492-SW4 https://developer.apple.com/library/mac/#documentation/DeveloperTools/Conceptual/LowLevelABI/140-x86-64_Function_Calling_Conventions/x86_64.html -Dmitry. On Tue, Feb 26,

Hi, Is there something wrong with my inline assembly below? *** target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.5" define void @"\01_SYSTEM_$$_SETMXCSR$LONGWORD"(i32 %p.w) nobuiltin { ; [71] procedure

On Sun, Jan 25, 2009 at 11:38:48AM +0100, Jean-Daniel Dupas wrote: > > Le 25 janv. 09 à 06:01, Jack Howarth a écrit : > > > After trying the recommended use of -O4 -fvisibility=hidden to > > compile xplor-nih with full LTO optimizations, I discovered three > > symbols become undefined... > > > > llvm-gcc-4 -O4 -fvisibility=hidden -o xplor xplor.o \ >

On Jun 16, 2009, at 1:17 PMPDT, Anton Korobeynikov wrote: > Hello, Aaron > >> Can I ask what platform ABI's are documented other than Itanium ? > I'd bet all platform ABI are more or less documented. > >> I need to get to understand PIC on x86, x86_64 and PowerPC for the >> COFF and MachO backends. > ABI is normally induced by platform, not by

Hi Jack, On Jan 25, 2009, at 10:00 AM, Jack Howarth wrote: > Doing that changes the error messages into a bus > error on the darwin linker. Pl. file bugzilla report (or radar) with a reproducible test case so that we can investigate this linker crash. As you know, one way to control symbol visibility is to use gcc's (inherited by llvm-gcc) visibility support. GCC supports, 1)

Hi all, I've been subscribed to this list on-and-off and always found it very helpful. I'm facing the problem of compiling a project in Objective C with LLVM in a Darwin environment. There is a certain Objective C protocol that appears in two .m files, and so the corresponding l_OBJC_PROTOCOL and l_OBJC_LABEL_PROTOCOL symbols appear in both .o files. The problem is that while these

> Message: 5 > Date: Mon, 26 Jan 2009 21:47:12 -0500 > From: "Jonathan S. Shapiro" <shap at eros-os.com> > Subject: [LLVMdev] PPC calling convention -- how to provide an > environment pointer? > To: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> > Message-ID: <1233024432.24380.11.camel at vmx> > Content-Type: text/plain > > This is

On Sat, 2012-05-12 at 00:47 -0500, Hal Finkel wrote: > On Tue, 01 May 2012 21:25:29 -0500 > Peter Bergner <bergner at vnet.ibm.com> wrote: > > By the strict letter of the 32-bit ABI, the save and restore of > > r31 at a negative offset of r1 is verboten. The ABI states the > > the stack space below the stack pointer is declared as volatile. > > I actually

Hello, Aaron > Can I ask what platform ABI's are documented other than Itanium ? I'd bet all platform ABI are more or less documented. > I need to get to understand PIC on x86, x86_64 and PowerPC for the COFF and MachO backends. ABI is normally induced by platform, not by architecture or object file format (however they can influence on it). 1. Windows is PIC by design. Google for

On Tue, 2009-01-27 at 08:59 -0800, Stuart Hastings wrote: > I assume you're talking about the 32-bit PowerPC. Also 64-bit, but the two register usage conventions are very close. Someone previously pointed out that R0 is usable as a scratch register, and the CTR can be used. CTR *must* be used for the branch destination out of the ASM trampoline. R0 ends up getting used a lot for constant

Anton, Sorry I have not replied earlier. Can I ask what platform ABI's are documented other than Itanium ? I need to get to understand PIC on x86, x86_64 and PowerPC for the COFF and MachO backends. Thanks, Aaron 2009/6/15 Anton Korobeynikov <anton at korobeynikov.info> > Hello, Aaron > > > Is there any overview or detailed socumentation on LLVM PIC ? > Did you

Hello, I am Shashidhar SR Working for Siemens Communication Software in Bangalore, INDIA as a Configuration Manager for Clearcase. I need some help regarding the samba configuration at our site. First Let me Explain our Environment: - We are Using samba 2.2.8a on Solaris 9. - We are using samba as an interop from Solaris 9 box to winnt/w2k/win-xp clients. - On Solaris we have installed IBM

Hi Everyone, I am Shashidhar G, M.S. Research Scholar at Indian Institute of Technology Madras working in the area of Program Analysis and Compiling for Parallelization. I am interested in working with the LLVM community for GSOC 2016. I looked at the Open projects and i am interested to work in the area of Alias Analysis. I have implemented a simple version of Andersen's Analysis as LLVM

Is the Wx:TaskBarIcon supported under OS X? I can''t seem to get it working. My code works under Windows, but not OS X. I thought it was something I was doing, so I tried the bigdemo.rb sample and that doesnt'' seem to like OS X either. I''m running OS X 10.5 with wxRuby 1.9.5 gem and ruby 1.8.6. -dave -- David Grandinetti (315) 569 2594

Looking forward to these changes! Thanks for working on it. On Fri, Oct 11, 2013 at 10:32 PM, Bill Wendling <isanbard at gmail.com> wrote: > Hi Dmitry, > > I can try my best, but it would be a bit tricky to get it all finished by > then... > > -bw > > On Oct 11, 2013, at 4:10 AM, Dmitry Babokin <babokin at gmail.com> wrote: > > Bill, > > Are there

Hi, We have an architecture where the indirect move instruction implicitly increments the pointer value after the move. We have Instruction format and pattern for this type of instructions. How to encode the information that the pointer is incremented? Thanks and regards, Shashidhar

Hi Hal, Our Architecture has indirect move instruction which increments the pointer implicitly and the target only has i8 type values. So the load of i16 will be converted to two i8 target loads wherein after the first load instruction, the pointer to the first i8 address will automatically increment to point to the next i8 value. So the post increment nature is in the Target. A normal

Bill, Are there any chances that you complete it before 3.4 is branched? On Thu, Oct 10, 2013 at 10:16 PM, Bill Wendling <isanbard at gmail.com> wrote: > On Oct 10, 2013, at 4:22 AM, Dmitry Babokin <babokin at gmail.com> wrote: > > > Bill, > > > > Thanks for answering. To make sure that we are on the same page, let's > agree on definitions :) Here, by

FYI: http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-October/066389.html Please read and let me know you comments. -bw On Oct 11, 2013, at 2:47 PM, Dmitry Babokin <babokin at gmail.com> wrote: > Looking forward to these changes! Thanks for working on it. > > > On Fri, Oct 11, 2013 at 10:32 PM, Bill Wendling <isanbard at gmail.com> wrote: > Hi Dmitry, > > I

Nadav, You are absolutely right, it's ISPC workload. I've checked SSE4 and it's also severely affected. We use intrinsics only for conversion <N x i32> <=> i32, i.e. movmsk.ps. For the rest we use general LLVM instructions. And I actually would really like to stick this way. We rely on LLVM's ability to produce efficient code from general LLVM IR. Relying on