Displaying 20 results from an estimated 8000 matches similar to: "[LLVMdev] localstatckallocation pass"
2013 Jan 08
2
[LLVMdev] mips16 hard float puzzle
For example:
/home/rkotler/llvm/install/bin/llc -mcpu=mips16 hf16_2.ll -march=mipsel
-relocation-model=pic -o hf16_2.s -O3 -mips16-hard-float -soft-float
On 01/04/2013 07:45 PM, Eli Friedman wrote:
> On Fri, Jan 4, 2013 at 6:28 PM, reed kotler <rkotler at mips.com> wrote:
>> On 01/04/2013 06:08 PM, Eli Friedman wrote:
>>> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler
2013 Jan 11
2
[LLVMdev] adding IR attributes to llvm
Yes, you could have mips16 and fastcc.
Mips16 just means that processor mode to execute that function is "mips16".
So in a mips16 designated function, I will just emit mips16 instructions
and in a "nomips16"
function, just emit normal mips32 instructions.
I tend to call this "mips32" normal mode, "standard encoding" because in
reality the processor is
2013 Jan 05
0
[LLVMdev] mips16 hard float puzzle
On Fri, Jan 4, 2013 at 6:28 PM, reed kotler <rkotler at mips.com> wrote:
> On 01/04/2013 06:08 PM, Eli Friedman wrote:
>>
>> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com> wrote:
>>>
>>> I'm working on mips16 hard float which at a first approximation is just
>>> soft
>>> float but calls different library
2013 Jan 11
0
[LLVMdev] adding IR attributes to llvm
I think that Bill Wendlings new attribute implementation would allow me
to do this but it is not ready yet.
Maybe it's okay to just add them to the list of function attributes as I
suggested.
But in the end, someone has to approve the checkin.
On 01/11/2013 07:35 AM, Reed Kotler wrote:
> Yes, you could have mips16 and fastcc.
>
> Mips16 just means that processor mode to execute
2013 Jan 08
0
[LLVMdev] mips16 hard float puzzle
On Mon, Jan 7, 2013 at 4:16 PM, reed kotler <rkotler at mips.com> wrote:
> On 01/04/2013 07:45 PM, Eli Friedman wrote:
>>
>> On Fri, Jan 4, 2013 at 6:28 PM, reed kotler <rkotler at mips.com> wrote:
>>>
>>> On 01/04/2013 06:08 PM, Eli Friedman wrote:
>>>>
>>>> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com>
2012 Sep 06
1
[LLVMdev] micro mips/mips32
Micro mips is really 100% .s compatible with mips32.
There are no register field size constraints and such.
It's a strict superset of mips32. For the gcc port, the assembler is
basically the only thing we changed.
The gcc port was just adding the ".micromips" directive to the .s file
and maybe some tiny
driver work.
That is the quandary.
The entire .td file would have to be
2013 Jan 08
2
[LLVMdev] mips16 hard float puzzle
On 01/04/2013 07:45 PM, Eli Friedman wrote:
> On Fri, Jan 4, 2013 at 6:28 PM, reed kotler <rkotler at mips.com> wrote:
>> On 01/04/2013 06:08 PM, Eli Friedman wrote:
>>> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com> wrote:
>>>> I'm working on mips16 hard float which at a first approximation is just
>>>> soft
2013 Jan 05
4
[LLVMdev] mips16 hard float puzzle
On 01/04/2013 06:08 PM, Eli Friedman wrote:
> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com> wrote:
>> I'm working on mips16 hard float which at a first approximation is just soft
>> float but calls different library routines. Those different library routines
>> are just an implementation (in mips32 mode) of soft float using mips32
>>
2013 Mar 27
1
[LLVMdev] LLVM pass question
So the switching between mips16 and mips32 on a per function basis seems
to basically be working except that asm printer has some kind of
issue here.
I'm debugging that now.
I get this:
lc: /home/rkotler/workspace/llvmpb6/include/llvm/MC/MCStreamer.h:224:
void llvm::MCStreamer::SwitchSection(const llvm::MCSection*): Assertion
`Section && "Cannot switch to a null
2012 Sep 06
0
[LLVMdev] micro mips/mips32
My understanding was that micro mips was similar to Thumb2, in that the smaller encodings have constraints on which registers can be read/written, because of the narrowing of the register fields in the encoding.
If that's the case, then it definitely makes sense to model the micro mips instruction set as distinct from the mips32 instruction set, in basically the same way that Thumb2 is done.
2013 Mar 27
0
[LLVMdev] LLVM pass question
This seems to work okay.
I register both the Mips16 and non Mips16 passes of the instruction
selector and then those return false if they are not supposed to be running.
Make-check at least passes in this case.
So in principle turn on the dual mode now and debug whatever misc is left.
For this I insert another pass before the mips16 and non mips16 passes.
On 03/27/2013 10:19 AM, Reed Kotler
2013 Feb 06
0
[LLVMdev] register scavenging
No. forward() is working correctly. All virtual register references must be resolved before calling it.
-Jim
On Feb 5, 2013, at 4:05 PM, Reed Kotler <rkotler at mips.com> wrote:
> So what I realized is that you can't use the simple scavenger trick where you create the virtual register and use the more advanced features.
>
> This is because you can't call forward() in any
2013 Mar 27
2
[LLVMdev] LLVM pass question
What I am thinking of now is to just register the MIPS116 and MIPS32
DAGToDAGISel passes and then within run on machine function, I can just
return if the current mode indicates that mips16 is needed for example,
so the run on machine function for Mips32 would return immediately.
On 03/27/2013 10:05 AM, Reed Kotler wrote:
> I guess another way to do this is to just register both passes for
2012 Sep 06
2
[LLVMdev] micro mips/mips32
The problem is that everything about the mips32 and micro mips 16
instruction is the same, aside from the encoding in to binary.
Seems like maybe we need to extend the notion of an instruction so that
it can have alternate encodings depending on subtarget.
On 09/05/2012 08:28 PM, Jim Grosbach wrote:
> The instructions are defined by their encodings, not the assembly syntax. You want
2013 Jan 05
0
[LLVMdev] mips16 hard float puzzle
On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com> wrote:
> I'm working on mips16 hard float which at a first approximation is just soft
> float but calls different library routines. Those different library routines
> are just an implementation (in mips32 mode) of soft float using mips32
> hardware instructions. This part is already done. (mips16 mode has no
2013 Jul 25
1
[LLVMdev] static functions and optimization
Seems like -femit-all-decls partially works around this.
But I would still like to solve the real problem of creating a function
which is local/static but which cannot be thrown away by the optimizer
if not referenced.
On 07/24/2013 04:07 PM, Reed Kotler wrote:
> Maybe there is some attribute I can add this will not allow the function
> to be discarded.
>
> On 07/24/2013 03:45 PM,
2013 Feb 06
2
[LLVMdev] register scavenging
So what I realized is that you can't use the simple scavenger trick
where you create the virtual register and use the more advanced features.
This is because you can't call forward() in any form if there are
virtual registers being used by any of the instructions in the basic
block. This will cause forward to fail.
Maybe this is a bug in forward()
On 02/05/2013 02:51 PM, Reed Kotler
2012 Sep 21
2
[LLVMdev] mips16 puzzle
Actually, SP is already not in the mips 16 register class but there is
some C++ code that is common to mips32, mips64 and mips16 that is
wanting to use SP. It's kind of awkward but does work except in this
case of load/store haflword and byte to stack objects.
Maybe I'm shooting myself in the foot there. I don't know that code too
well so maybe I need to look into it.
There are
2012 Sep 24
0
[LLVMdev] mips16 puzzle
On Sep 20, 2012, at 11:44 PM, Reed Kotler <rkotler at mips.com> wrote:
> Actually, SP is already not in the mips 16 register class but there is some C++ code that is common to mips32, mips64 and mips16 that is wanting to use SP. It's kind of awkward but does work except in this case of load/store haflword and byte to stack objects.
>
ARM has a similar problem. The InstrInfo
2012 May 14
0
[LLVMdev] getMinimalPhysRegClass
Reed,
On May 14, 2012, at 3:45 PM, reed kotler <rkotler at mips.com> wrote:
> On 05/14/2012 02:42 PM, Jakob Stoklund Olesen wrote:
>> On May 14, 2012, at 2:28 PM, reed kotler wrote:
>>
>>> I'm not using getMinimalPhysRegClass. Some target independent code is using it.
>> Probably PEI.
>>
>>> It makes trouble for us and I would like to