similar to: [LLVMdev] constants in text section for mips 16

Hi Reed, > I'm wondering if there is already some mechanism where I can assign literals > to the text section and get a label for where it has been stored. I think putting them in the text section is reasonably simple, though doesn't have a generic "pleasePutConstantsAfterFunctions()" call in LLVM. A good place to start would be the reverse of my recent patch to AArch64

Why did you take out the constant island code for Arm 64? Just did not need it? On 02/21/2013 12:01 PM, Tim Northover wrote: > Hi Reed, > >> I'm wondering if there is already some mechanism where I can assign literals >> to the text section and get a label for where it has been stored. > > I think putting them in the text section is reasonably simple, though >

Hi, I'd like to generate constants inside .text in order to use ip-relative loads, when the code model is "large". How can I do this? (I'm on X86_64 linux) Thank you. - Elena --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the

Hi, I'm building a new backend which can only load very limited range of imm. So I decided to use constant pool, and place constant pool entries close enough to instructions use the entries (we have very limited range PC-relative memory load). However, lld & llc output the object files that gather all constant pool entries into one section. How can I make them mix these entries into code

Currently llvm crashes on following code, run through llc: declare void @llvm.experimental.stackmap(i64, i32, ...) define void @foo() { tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 0, i32 0, i64 9223372036854775807) ret void } The issue is that 9223372036854775807 (decimal for 0x7fffffffffffffff) is the "empty key" for an int64_t, and in

Hi there, I've created a bug on llvm: http://www.llvm.org/bugs/show_bug.cgi?id=9582 Basically, ARM, Thumb and data mapping symbols should have been exported in the ELF file, so the linker can work correctly. I can do the change and create some test cases, but I haven't been paying much attention to recent MC developments. Is ArmAsmPrinter the place to change for that, or is there an MC

Hi Elena, > I’d like to generate constants inside .text in order to use ip-relative > loads, when the code model is “large”. I don't think this is a sequence the x86 backend supports at the moment, but it is how ARM handles its constant-pools. The outline is that you have a pass which looks through a functions constpool uses and emits a pseudo-instruction for each, which is then

Hi All, In SVN head, MipsISelDAGToDAG.cpp has the following optimization: // Operand is a result from an ADD. if (Addr.getOpcode() == ISD::ADD) { // When loading from constant pools, load the lower address part in // the instruction itself. Example, instead of: // lui $2, %hi($CPI1_0) // addiu $2, $2, %lo($CPI1_0) // lwc1 $f0, 0($2) // Generate: //

On Mar 29, 2011, at 8:44 AM, Renato Golin wrote: > Hi there, > > I've created a bug on llvm: > > http://www.llvm.org/bugs/show_bug.cgi?id=9582 > > Basically, ARM, Thumb and data mapping symbols should have been > exported in the ELF file, so the linker can work correctly. > > I can do the change and create some test cases, but I haven't been > paying

I have created a small ll file to reproduce the problem. I used the intrinsic function llvm.arm.space to introduce space between the beginning of the code and the jump table. If the first argument of llvm.arm.space is higher than INT_MAX ( *2147483647)*, then the bug is hit. Lower or equal to that value, it passes. It looks like a precision issue. Does this sound familiar to someone? ; ModuleID =

> De : Joerg Sonnenberger [mailto:joerg at britannica.bec.de] > > Well, MCFixup is what a relocation is represented as internally. They get > resolved to a fixed value and replaced, if evaluateAsAbsolute is true. > Hi Joerg, Actually it fails to get resolved to a fixed value. When I compile to .o then objdump it I can see that a symbol holding the constant value was created in

Hi, I have kept working on this and found the following (as llvm 3.5): 1) In the function MCObjectStreamer::EmitInstruction there is a check for the instruction being relaxable or not: if (!Assembler.getBackend().mayNeedRelaxation(Inst)) { EmitInstToData(Inst, STI); return; } At this stage, the instruction as been already selected to be ARM::ADR. The call to mayNeed 2015-07-07 18:06

Today I updated to trunk the toolchain for my work developing on Cortex-M4F. I was super excited to see three commits by Tim Northover that actually attempt to improve the machine code generation for my target, or any ARM target for that matter (as opposed to other important work on compiler correctness or architectural elegance or formatting comment white-space, I mean). Is he alone or are

LLVM Weekly - #46, Nov 17th 2014 ================================ If you prefer, you can read a HTML version of this email at <http://llvmweekly.org/issue/46>. Welcome to the forty-sixth issue of LLVM Weekly, a weekly newsletter (published every Monday) covering developments in LLVM, Clang, and related projects. LLVM Weekly is brought to you by [Alex Bradbury](http://asbradbury.org).

Hi Gary, On 3 December 2013 22:01, Gary Fuehrer <gfuehrer at defiant-tech.com> wrote: > The subject of two of his commits dealt with substituting MOVW/MOVT pairs > for an LDR and a lit-pool. Isn't this what MachineConstantPool and > ARMConstantIslandPass was all about? Both are essential components to using lit-pools: the MachineConstantPool is just LLVM's underlying

> > > > I was mucking around in FastISel, and was surprised to see the test > > > > llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll > > > > failed. This was surprising because it specifies -fast-isel=false. > > > > > > > > Does the Mips code generator use fast-isel even when you ask it not > to? > > > > Thanks,

Hi Renato, Thanks for the thoughtful reply. Please find my thoughts below. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation From: Renato Golin [mailto:renato.golin at linaro.org] Sent: Friday, October 25, 2013 1:11 PM To: David Peixotto Cc: LLVM Dev; Logan Chien; Gabor Ballabas; Rafael Espíndola; Richard Barton; Amara Emerson Subject:

> > I was mucking around in FastISel, and was surprised to see the test > > llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll > > failed. This was surprising because it specifies -fast-isel=false. > > > > Does the Mips code generator use fast-isel even when you ask it not to? > > Thanks, > > --paulr > > This seems to be an all-targets bug.

On Oct 25, 2013, at 3:53 PM, David Peixotto <dpeixott at codeaurora.org> wrote: > Hi Renato, Thanks for the thoughtful reply. Please find my thoughts below. > > -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation > > > From: Renato Golin [mailto:renato.golin at linaro.org] > Sent: Friday, October 25, 2013 1:11 PM

From: Jim Grosbach [mailto:grosbach at apple.com] Sent: Friday, October 25, 2013 4:31 PM To: David Peixotto Cc: Renato Golin; LLVM Dev Subject: Re: [LLVMdev] Add support for ldr pseudo instruction in ARM integrated assembler On Oct 25, 2013, at 3:53 PM, David Peixotto <dpeixott at codeaurora.org> wrote: Hi Renato, Thanks for the thoughtful reply. Please find my thoughts below.