Displaying 20 results from an estimated 600 matches similar to: "[LLVMdev] Problem to run SPEC2006"
2013 Feb 19
1
[LLVMdev] Problem to run SPEC2006
Actually I am trying to run SPEC2006 through the Makefiles provided with
LLVM Test Suite, so I think it should work properly...
On 18 February 2013 15:49, Adhemerval Zanella
<azanella at linux.vnet.ibm.com>wrote:
> I can't really tell what is happening based on this output, but 'make' is
> not the right way
> to build SPECcpu2006 components. You need to do either by
2013 Feb 18
0
[LLVMdev] Problem to run SPEC2006
I can't really tell what is happening based on this output, but 'make' is not the right way
to build SPECcpu2006 components. You need to do either by using the supplied 'runspec'
command with '-build' action directive or to issue the 'specmake' (which is a
make adjusted by spec.org) on the build component folder.
I can build 433.milc on PPC64 with clang without
2013 Mar 03
1
[LLVMdev] Can a Function Pass require a Module Pass?
Dear LLVMers,
I am implementing a Function Pass and I would like to use analysis obtained
from a Module Pass. Some extracts of my code look like that:
struct MyPass : public FunctionPass {
static char ID;
MyPass() : FunctionPass(ID) {
PADriver &PD = getAnalysis<AModulePass>();
...
virtual void getAnalysisUsage(AnalysisUsage &AU) const{
2013 Jan 21
1
[LLVMdev] Testing canaries
Dear LLVMers,
I am trying to measure the performance overhead (if any) of the
canaries that clang inserts in the code. I would like to do this
automatically, using the LLVM test infra-structure. However, I am not sure
if that is possible. Could someone tell me which flags in the
TEST.nightly.Makefile script, (or any other script) I must change to have
this done? Usually I insert canaries with
2011 Apr 12
1
[LLVMdev] Problems with test-suite
Hello, all-
I am having trouble getting the test suite set up with my download of
SPEC2006. I downloaded and installed llvm-gcc, checked out a copy of
test-suite in llvm-2.8/projects, and then configured and made llvm:
./configure --enable-debug-runtime --disable-optimized
--enable-spec2006=/home/jamiemmt/speccpu2006 --with-externals=/home/jamiemmt
make
The configure script found the SPEC
2009 May 29
2
[LLVMdev] make TEST=ipodbgopt in sqlite3: problem with TCLSH
On Linux, when I run "make TEST=ipodbgopt" in
MultiSource/Applications/sqlite3 I get:
make[4]: Entering directory
`/home/foad/llvm/poo/build/test-suite/MultiSource/Applications/sqlite3'
Compiling shell.c to Output/shell.bc
/home/foad/svn/llvm-project/test-suite/trunk/MultiSource/Applications/sqlite3/speedtest.tcl
make[4]: execvp:
2007 May 04
3
[LLVMdev] llvm-test make problems
Reid Spencer wrote:
> Have you modified the makefile in any way? Note that sse.expantfft.bc should be sse.expandfft.bc
no, did'nt change it.
the typo before seems to be an error while copying from the terminal.
i've cleaned everything and tried again. this is the messsage:
[brandner:/localtmp/brandner/dev/llvm-test:529] make -j1 TEST=nightly
2>&1 | tee report.nightly.raw.out
2015 Sep 03
2
LiveInterval and Loop Info
Hello to all LLVM Developers.
Given a object from a LiveInterval class, is there any way to know if this
Live Interval is part or is inside a loop?
Att
--
Natanael Ramos
Membro do corpo discente de Ciência da Computação pelo Instituto Federal de
Minas Gerais - Campus Formiga
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2020 Aug 18
7
[RFC] Switching to MemorySSA-backed Dead Store Elimination (aka cross-bb DSE)
Hi,
Over the past six months, a MemorySSA-backed DSE implementation has been added to LLVM and it now covers almost all cases the existing DSE implementation does, plus adding a major new capability: eliminating stores across basic blocks. Thanks everyone involved with reviews, testing & patches!
I think now would be a good time to start working towards switching to use MemorySSA-backed DSE
2014 Sep 09
5
[LLVMdev] Please benchmark new x86 vector shuffle lowering, planning to make it the default very soon!
Hi Chandler,
Thanks for fixing the problem with the insertps mask.
Generally the new shuffle lowering looks promising, however there are
some cases where the codegen is now worse causing runtime performance
regressions in some of our internal codebase.
You have already mentioned how the new shuffle lowering is missing
some features; for example, you explicitly said that we currently lack
of
2013 Jan 28
0
[LLVMdev] Testing canaries
Dear Duncan,
thank you very much. I have been able to use it now, via the following
command line:
clang -emit-llvm -c -fstack-protector canary.c -o canary.bc
llc -print-before=stack-protector -print-after=stack-protector -o
canary.s < canary.bc
Thank you again,
Izabela Maffra.
On 26 January 2013 15:55, <llvmdev-request at cs.uiuc.edu> wrote:
> Send LLVMdev mailing
2015 Sep 04
2
LiveInterval and Loop Info
Thanks Matthias
I can also use the method intervalIsInOneMBB() from LiveIntervals class to
relate a LiveInterval to a MachineBasicBlock, right?
Em 04/09/2015 2:26 PM, "Matthias Braun" <mbraun at apple.com> escreveu:
> There is no direct support for this, but you can use
> LiveIntervalAnalysis::getMBBStartIndex()/getMBBEndIndex()/getMBBFromIndex()
> to relate the
2015 Sep 03
2
LLVM and strict SSA
Hello to all LLVM Developers.
The LLVM IR is in strict SSA form (i.e. every variable is defined before it
is used along every path from the entry to exit point)?
According to the documentation, currently the LLVM IR is in the SSA form,
but I don't see additional information about *strict* SSA form.
The strict SSA form provide opportunities of optimization in register
allocation, because is
2007 Sep 18
0
[LLVMdev] 2.1 Pre-Release Available (testers needed)
On Saturday 15 September 2007, Tanya Lattner wrote:
> 2) Download llvm-2.1, llvm-test-2.1, and the llvm-gcc4.0 source.
> Compile everything. Run "make check" and the full llvm-test suite
> (make TEST=nightly report).
I tried to do this, but ran into trouble.
LLVM itself compiled fine.
GCC compilation is broken when Java support is enabled. I can file a detailed
bug report
2015 Jul 09
3
[LLVMdev] PHI Elimination in Register Allocation Pass
Good Afternoon.
I am a Computer Science undergraduate student in Brazil and as completion
of course work, I am developing an register allocator, using the
infrastructure of the LLVM.
To accomplish this task, I have based my implementation in allocators
already implemented in LLVM. But a question came to me while I was
researching in books and articles of compiler theory and own documentation
of
2012 Jun 05
2
[LLVMdev] [PATCH] add x32 psABI support
If you are interesting to play around X32, you may refer to http://sourceware.org/glibc/wiki/x32 to bootstrap a local environment on Linux.
Yours
- Michael
-----Original Message-----
From: cfe-commits-bounces at cs.uiuc.edu [mailto:cfe-commits-bounces at cs.uiuc.edu] On Behalf Of Liao, Michael
Sent: Monday, June 04, 2012 5:09 PM
To: llvm-commits at cs.uiuc.edu; cfe-commits at cs.uiuc.edu
2015 May 20
2
[LLVMdev] Implement a Register Allocator in LLVM
I'm working on my project for completion undergraduate courses, consisting
of an experimental analysis of registers allocation algorithms. For this
task, I am using the set of tools from the LLVM project.
However, I have read the documentation of the LLVM project and not yet
found a way to put the pieces of the puzzle together. So far I know:
- As passes work as engage them to LLVM and
2015 Sep 01
2
Spilling Virtual Registers
Hello to all LLVM developers.
I'm developing a register allocator using LLVM, my allocator has a local
search phase: given a solution (assignment of virtual registers to physical
registers or memory) generated in the first phase of the algorithm, some
movements are applied to this solution in order to find a better solution.
To apply such movements, I need to unassign a virtual register from
2017 Jan 30
4
(RFC) Adjusting default loop fully unroll threshold
Currently, loop fully unroller shares the same default threshold as loop
dynamic unroller and partial unroller. This seems conservative because
unlike dynamic/partial unrolling, fully unrolling will not affect
LSD/ICache performance. In https://reviews.llvm.org/D28368, I proposed to
double the threshold for loop fully unroller. This will change the codegen
of several SPECCPU benchmarks:
Code
2013 Feb 12
3
[LLVMdev] RE : Is there any llvm neon intrinsic that maps to vmla.f32 instruction ?
On 12 February 2013 16:56, Sebastien DELDON-GNB <sebastien.deldon at st.com>wrote:
> If this helps taking your decision, there are at least two benchmarks for
> which disabling vmlx-forwarding makes a significant difference.
>
I think Evan's worry was to base this decision on visible and
comprehensible benchmarks, such as the test-suite.
If I get lucky I may be able to run