similar to: [LLVMdev] implicit register usage

Hi Jim, One thing that seems strange to me is that if do a BuildMI, if you put a register inside the first parens, then it will treat it as a def, but if you just .addReg it won't (by default), even though it should know from the instruction definition. Seems like it should do that. Why would you want it to not do that? Reed On 02/18/2013 01:22 PM, Jim Grosbach wrote: > Hi Reed,

Hi Reed, The .td file "Defs = …" should be sufficient. The implicit uses and implicit defs are part of the MCInstrDesc data structure, which is shared by all instances of a given instruction. -Jim On Feb 17, 2013, at 2:22 PM, reed kotler <rkotler at mips.com> wrote: > If I put in my tablegen td file that a certain instruction implicitly sets a register, do I need to also do

I'm not sure. It certainly seems reasonable to me that the building could/should set default Define flags on operands based on the MCInstrDesc. Dunno why it doesn't. -Jim On Feb 19, 2013, at 7:14 PM, reed kotler <rkotler at mips.com> wrote: > Hi Jim, > > One thing that seems strange to me is that if do a BuildMI, if you put a register inside the first parens, then it

On 02/15/2013 03:07 PM, Jakob Stoklund Olesen wrote: > On Feb 15, 2013, at 1:21 PM, Reed Kotler <rkotler at mips.com> wrote: > >> I want to have some functions that create machine instructions, not specifying which machine function or basic block or iterator they are part of. > All machine instructions must be created by a machine function. It provides the context for memory

I ended up settling on a scheme which I'm not completely happy with but it's the best I can see to do. const MCInstrDesc& AddiuSpImm(int64_t Imm) const; and then if (isInt<16>(-Remainder)) BuildMI(MBB, I, DL, AddiuSpImm(-Remainder)).addImm(-Remainder); So the AddiuSpImm choses which instruction description to use depending on the immediate value and then

On Feb 20, 2013, at 1:27 PM, Jim Grosbach <grosbach at apple.com> wrote: > > On Feb 20, 2013, at 1:22 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > >> >> On Feb 20, 2013, at 11:44 AM, Jim Grosbach <grosbach at apple.com> wrote: >> >>> I'm not sure. It certainly seems reasonable to me that the building could/should set default

On Feb 20, 2013, at 11:44 AM, Jim Grosbach <grosbach at apple.com> wrote: > I'm not sure. It certainly seems reasonable to me that the building could/should set default Define flags on operands based on the MCInstrDesc. Dunno why it doesn't. Once you move beyond the fixed operands, it can't be determined automatically if the added register should be a use or a def. But I

Reed, Couldn't you also use instruction scheduling classes and specify that the second instruction has a bypass from the first instruction? The scheduler should always schedule them together in that case. Micah > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On > Behalf Of reed kotler > Sent: Tuesday, September 17, 2013

I used the A9 schedule as an example: http://llvm.org/svn/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td The documentation could use more clarity, but this is how I was able to do it to always get two specific instructions to be scheduled together. ________________________________________ From: reed kotler [rkotler at mips.com] Sent: Tuesday, September 17, 2013 8:54 PM To: Micah Villmow

+the list again On Sep 17, 2013, at 3:48 PM, reed kotler <rkotler at mips.com> wrote: > On 09/17/2013 03:46 PM, Owen Anderson wrote: >> On Sep 17, 2013, at 3:08 PM, reed kotler <rkotler at mips.com> wrote: >> >>> Is there any way, except for using bundles, to force two instructions to be sequentially executed? >> What level of codegen are you working at?

On Feb 20, 2013, at 1:22 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Feb 20, 2013, at 11:44 AM, Jim Grosbach <grosbach at apple.com> wrote: > >> I'm not sure. It certainly seems reasonable to me that the building could/should set default Define flags on operands based on the MCInstrDesc. Dunno why it doesn't. > > Once you move beyond

On Feb 15, 2013, at 1:21 PM, Reed Kotler <rkotler at mips.com> wrote: > I want to have some functions that create machine instructions, not specifying which machine function or basic block or iterator they are part of. All machine instructions must be created by a machine function. It provides the context for memory allocation etc. > And then I want to use that result when adding

On 09/17/2013 04:51 PM, Micah Villmow wrote: > Reed, > Couldn't you also use instruction scheduling classes and specify that the second instruction has a bypass from the first instruction? The scheduler should always schedule them together in that case. > > Micah > I'm not sure exactly what you mean. Can you point me to an example of that? TIA. Reed >>

After discussions last night, I'm leaning towards going legit with all my pseudo expansions in Mips 16. Some I think I can clearly do by just putting in the proper side effects of implicit registers (T8 the condition code register as used by mips 16). But I'm still left with some pseudos that have jmp .+4 type instructions in them. The original Mips port was to Mips I and Mips I,

On 09/17/2013 03:52 PM, Owen Anderson wrote: > +the list again > On Sep 17, 2013, at 3:48 PM, reed kotler <rkotler at mips.com> wrote: > >> On 09/17/2013 03:46 PM, Owen Anderson wrote: >>> On Sep 17, 2013, at 3:08 PM, reed kotler <rkotler at mips.com> wrote: >>> >>>> Is there any way, except for using bundles, to force two instructions to be

That doesn't actually give you a guarantee that they won't be split up. Phases other than the scheduler may insert instructions in the middle of block (constant island pass, for example). Pseudo-instructions are the canonical answer to that problem. --Owen On Sep 17, 2013, at 11:09 PM, Micah Villmow <micah.villmow at smachines.com> wrote: > I used the A9 schedule as an

Some stuff did not get pasted in properly. static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, DebugLoc dl, const MipsSubtarget *Subtarget, const TargetInstrInfo *TII, bool isFPCmp, unsigned Opc) { //

I want to have some functions that create machine instructions, not specifying which machine function or basic block or iterator they are part of. And then I want to use that result when adding that instruction to a basic block. I'm pretty sure you can do this but we have not done this in the Mips port so far. We just use instruction builder. Anyone know how to do this best, or can point

This is the old MIPS I code that sort of does what I need to do. This seems really involved to do such a simple thing. Maybe there are now helper classes for this or some better example I can look at. I suppose I can mimick this if people say this just the correct way to do this in LLVM. static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,

You are trying to do a few different things here, and a uniform solution may not work for all of them. For a fixed instruction sequence, e.g. a special kind of move-and-branch sequence used for tail calls, you probably want a pseudo. If you are trying to combine arbitrary instructions together, e.g. Thumb IT blocks, you probably want to use bundles, even if the sequences are a fixed length. I