similar to: [LLVMdev] Deleting LiveVariables

How much of the work is done here? I'd be happy to do the phi elimination part, since I basically did that for StrongPhiElimination (RIP). IIRC you run into a lot of problems with NEON subregister defs, which might be fixed by your new direct LiveIntervals implementation. Cameron On Feb 8, 2013, at 3:41 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > I just enabled a new

On Feb 8, 2013, at 4:03 PM, Cameron Zwarich <zwarich at apple.com> wrote: > How much of the work is done here? I'd be happy to do the phi elimination part, since I basically did that for StrongPhiElimination (RIP). Any help would be appreciated. I did a bit of the easy stuff in 2-addr, it has a LIS = getAnalysisIfAvailable<LiveIntervals>() member that it sometimes updates. It

On Feb 8, 2013, at 4:20 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > On Feb 8, 2013, at 4:03 PM, Cameron Zwarich <zwarich at apple.com> wrote: > >> How much of the work is done here? I'd be happy to do the phi elimination part, since I basically did that for StrongPhiElimination (RIP). > > Any help would be appreciated. > > I did a bit of the

On Feb 8, 2013, at 4:37 PM, Cameron Zwarich <zwarich at apple.com> wrote: > On Feb 8, 2013, at 4:20 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > >> On Feb 8, 2013, at 4:03 PM, Cameron Zwarich <zwarich at apple.com> wrote: >> >>> How much of the work is done here? I'd be happy to do the phi elimination part, since I basically did that

On Feb 8, 2013, at 4:45 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > On Feb 8, 2013, at 4:37 PM, Cameron Zwarich <zwarich at apple.com> wrote: > >> I'll try doing that. Did you ever add a way to update LiveIntervals quickly after splitting an edge or will that have to finally be added? I can skip the critical edge splitting for now. > > That

Hi, In PR2193 LiveVariables runs out of memory on a 512M limit, after processing 11557 basicblocks. VirtRegInfo has ~180000 entries with ~700 bytes each. If I give it more memory (1.5G) it runs out of memory in LiveInterval. I don't see any easy solution to reduce memory usage, but should we optimize such a huge function at once? If the function is over some reasonable limit (5k

On Apr 13, 2008, at 1:28 PM, Török Edwin wrote: > Hi, > > In PR2193 LiveVariables runs out of memory on a 512M limit, after > processing 11557 basicblocks. > VirtRegInfo has ~180000 entries with ~700 bytes each. > If I give it more memory (1.5G) it runs out of memory in LiveInterval. Some of the information kept by LiveVariables are somewhat redundant and can be removed. I

I though LiveVariables may be invalidated by LiveIntervals, but it's declared not: void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const { AU.addPreserved<LiveVariables>(); AU.addRequired<LiveVariables>(); ... LiveInterval may coalesce virtual registers and remove identity moves instructions: bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {

Evan Cheng wrote: > On Apr 13, 2008, at 1:28 PM, Török Edwin wrote: > > >> Hi, >> >> In PR2193 LiveVariables runs out of memory on a 512M limit, after >> processing 11557 basicblocks. >> VirtRegInfo has ~180000 entries with ~700 bytes each. >> If I give it more memory (1.5G) it runs out of memory in LiveInterval. >> > > Some of the

Is LiveVariables updated correctly when TII->RemoveBranch and TII->InsertBranch are called in the following piece of code? - MachineBasicBlock::updateTerminator() line 307 of MachineBasicBlock.cpp: if (FBB) { // The block has a non-fallthrough conditional branch. If one of its // successors is its layout successor, rewrite it to a fallthrough // conditional branch.

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On May 2, 2011, at 3:51 PM, Akira Hatanaka wrote: > - vreg81's VarInfo: > Alive in blocks: 5, 6, 7, 8, 10, 12, 13, 19, > Killed by: > #0: J <BB#17> > > > As you can see, VarInfo vreg81 is killed by the unconditional jump instruction of BB#20 when it should be killed by the newly created conditional branch in BB#14 (BEQ). Is this a bug in

So what is the status about LiveVariables. Is there a plan to remove it? After searching in old lvm-dev-mails it is mentioned that LiveVariable still exists due to one pass needing it. And a comment in TargetPassConfig.cpp indicates that the pass in question is TwoAddressInstruction: // FIXME: Once TwoAddressInstruction pass no longer uses kill flags, // LiveVariables can be removed

Hi, I wonder when the preRASched pass is planned to be available? I wonder how one would best try to implement a pass in between RegCoalescer and RA. After RegCoalescer, the LiveVariables information seems broken (there are no Kills anywhere), and LiveVariables can't be rerun after SSA form is left. So, how could one rebuild LiveIntevals? For register allocation purposes - what would be the

LiveVariables gives you something like liveness analysis: where each variable is alive, that is, across each basic blocks, where it is defined, and where it is killed. LiveIntervals gives you a linear representation of the variables as a set of intervals. Yes, it handle holes in the live ranges. There is a very nice description of these analysis and related data structures here:

Fernando Magno Quintao Pereira wrote: > LiveVariables gives you something like liveness analysis: where each > variable is alive, that is, across each basic blocks, where it is defined, > and where it is killed. If I read this correctly, it means that at each instruction there's a list of live variables? I'm trying to figure out how to get at this information to build the

Hi (Jakob), in reference to the prior message below, I have the following follow-up questions, as I also need a scheduling pass prior to regalloc. I need to do this in order to set VLIW-flags, so that the RA is aware of several MI's per cycle with a redefined LiveRange::overlap-function. On a multiple-issue cycle, a register that gets killed can be reused by another MI - these live ranges do

I'm debugging a problem with a custom pass and I was surprised to discover that LiveIntervalAnalysis depends on PHIElimination. Why is that so? Intervals could be useful for all sorts of things beyond register allocation. Just curious. Is there something about the design of LiveIntervals that it needs the out-of-SSA conversion? -Dave

On 4/3/07, David Greene <greened at obbligato.org> wrote: > > Toward a better register allocator, I'm attempting to understand > the dataflow information available to the allocator. > > What's the difference between LiveInterval information and LiveVariable > information? If a LiveInterval is based on a linear ordering of > the machine instructions, isn't it

Hello LLVM developers, I have a few questions regarding the passes that are run after instruction selection and before register allocation. I am writing a scheduling pass (modulo scheduling). Before I ask my questions, I will first try to explain the approach I am taking. - Currently, I am running the passes in the following order. (-debug-pass=Structure output) Remove unreachable machine