similar to: [LLVMdev] Incorrect Simple pattern matching in lib/CodeGen/IfConversion.cpp

Evan, et al., I've come across a small issue when using the if conversion pass in PPC to generate conditional returns. Here's a small example: ** Before if conversion ** BB#0: derived from LLVM BB %entry %R3<def> = LI 0 %CR0<def> = CMPLWI %R3, 0 BCC 68, %CR0, <BB#3> Successors according to CFG: BB#3(16) BB#1(16) BB#1: derived from LLVM BB

On Tue, Jan 10, 2017 at 2:31 AM, Peter A Jonsson <pj at sics.se> wrote: > Hi Kyle, > > my apologies for mailing you directly but it seems new user creation is > disabled on the llvm bugzilla. > > We sometime lose edges during IfConversion of diamonds and it’s not > obvious how to reproduce on an upstream target. The documentation for > HasFallThrough says *may*

Hi All, How can I run the IfConversion pass in JIT to optimize my code for ARM as a Target Architecture? -- View this message in context: http://llvm.1065342.n5.nabble.com/Machine-level-IfConversion-for-ARM-tp69513.html Sent from the LLVM - Dev mailing list archive at Nabble.com.

On Tue, Oct 10, 2017 at 4:48 PM, Friedman, Eli via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 10/9/2017 3:10 AM, Gaël Jobin via llvm-dev wrote: > > Hi all, > > I got a silly bug when compiling our project with the latest Clang. Here's > the outputted assembly: > > tst r3, #255 > strbeq r6, [r7] > ldreq r6, [r4, r6, lsl #2] > strne r6, [r7, #4]

Assume an architecture that has multiple condition code registers, e.g., powerpc. Now assume that there are predicate instructions like thumb2, but can specify which condition code register they refer to. Now also assume that these predicate instructions themselves are predicatible, if executed they change the current predication state. Can LLVM handle multiple levels of predication? When is

Hi all, If you have an out of tree target and use the IfConverter be aware of a new API call "getPredictationCost“ that you might want to implement: After commit r191671: IfConverter: Use TargetSchedule for instruction latencies For targets that have instruction itineraries this means no change. Targets that move over to the new schedule model will be able to use the new

Hello, I have a few questions about applying the IfConversion pass to my out-of-tree target. (1) Is it true that the IfConversion pass may only run after register allocation? I often encounter this bad scenario, and I think it could be entirely avoided if IfConversion ran before register allocation: the block-to-be-predicated contains load-immediate (LI) instructions. The LI instructions

Hi all, I got a silly bug when compiling our project with the latest Clang. Here's the outputted assembly: > tst r3, #255 > strbeq r6, [r7] > ldreq r6, [r4, r6, lsl #2] > strne r6, [r7, #4] > ldr r6, [r4, r6, lsl #2] > bx r6 For the code to execute correctly, either the _ldr_ should be a _ldrne_ instruction or the _ldreq_ instruction should be removed. The error seems to

Hi. On our system we have a problems with recursive IfConversion algorithm. Here is the patch for making it loop-based. Or do I need to send it to some other mail-list? -- Best regards, Andrew Zhogin. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130701/f526e1f0/attachment.html> -------------- next

I was hoping to get feedback on this proposal formatted as a patch. I'd like to teach AnalyzeBranch to handle conditional returns on PPC, but the currently documented API for AnalyzeBranch doesn't support it. I propose the following enhancement to the API so that I can teach AnalyzeBranch about conditional return instructions. ---------- Forwarded message ---------- From: Kyle Butt

Hi all, I am using llvm backend to generate binary for a specific accelerator. I would like to convert instructions into predicated form when instructions are still in SSA form. It looks like that ifconversion execution flow is different when instructions are in SSA form. However, I am encountering many problems (specially with registers) when I use it before register allocation. I was wondering

Hi, I am trying to implement support for an if-conversion pass in a backend for the ADRES CGRA architecture. >From studying the existing IfConversion pass, I observed the following: - The PredicateInstruction method is meant to insert guards into conditional instructions. - This method assumes that one will be able to get the predicate from the conditional branch instruction on which

I need to do some analysis, in which I have to selectively convert IFs. I am trying to find a way to call this optimization pass from the JIT code, thus I can decide which branches to convert and which to keep. Apparently I cannot do this using a pass manager. -- View this message in context: http://llvm.1065342.n5.nabble.com/Machine-level-IfConversion-for-ARM-tp69513p69622.html Sent from the

The unchecked assertion that the same register is not added multiple times to the MBB::LiveIn list isn't being respected. Could we add an assertion to check for it? ==== //dwarc/Tools/MetaWare/Toolset/main/dev/llvm/include/llvm/CodeGen/MachineBasicBlock.h#6 - /remote/arctools/marksl/marksl_1/llvm/include/llvm/CodeGen/MachineBasicBlock.h ==== 295,298d294 < /// addLiveIn - Add the

Hi all, I've been investigating a machine verifier failure on the attached testcase, and I'm tempted to say the verifier is wrong and should accept it. Skip the description for the proposed change. On AArch64, the verifier complains with: *** Bad machine code: MBB exits via unconditional branch but doesn't have exactly one CFG successor! *** - function: t4 - basic

Hi, it seems to be generally a bad idea to enable vectorization of conditional stores on SystemZ, because it will cost extra instructions both to 1. extract compare result element 2. Do a test-under-mask instruction on that element 3. conditional branch past the store block. Ideally, I would like to adjust the cost for the vector compare. I am not sure if this is feasable since I would need

On Wed, Oct 31, 2012 at 09:13:43PM +0100, Bjorn De Sutter wrote: > Hi all, > > I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we

Is LiveVariables updated correctly when TII->RemoveBranch and TII->InsertBranch are called in the following piece of code? - MachineBasicBlock::updateTerminator() line 307 of MachineBasicBlock.cpp: if (FBB) { // The block has a non-fallthrough conditional branch. If one of its // successors is its layout successor, rewrite it to a fallthrough // conditional branch.

On 17 March 2017 at 16:34, Hal Finkel <hfinkel at anl.gov> wrote: > In general, this is true everywhere. In a large vectorized loop, this cost > may well be worthwhile. The idea is that the cost model should account for > all of these costs. If it doesn't properly, we should fix that. Isn't this only worth when the SIMD instructions can be conditionalised per lane? I

I am working on a back end for an architecture whose jump via table instruction includes the range check. If the index is out of range, the jump table instruction just falls through. I implemented a pass to remove the range check generated before the jump table instruction because it is superfluous. This causes as assertion in MachineBlockPlacement.cpp: