similar to: [LLVMdev] ARM c++ exceptions handling not working with clang/llvm-3.2?

Displaying 20 results from an estimated 1000 matches similar to: "[LLVMdev] ARM c++ exceptions handling not working with clang/llvm-3.2?"

2011 Aug 05
0
[LLVMdev] RFC: Exception Handling Rewrite
On Aug 5, 2011, at 10:57 AM, Peter Lawrence wrote: > Bill, > ooops, yes, I described the meaning of "throw(A)" backwards, I thought that might be the case. :) > but I still > think my example shows why you cannot merge LandingpadInst while > inlining because multiple filter-lists on a LandingpadInst don't make sense. > > Perhaps I'm reading your
2011 Jul 28
0
[LLVMdev] LLVMdev Digest, Vol 85, Issue 50
On Jul 28, 2011, at 2:22 PM, Peter Lawrence wrote: > John, > I'm still not sure what you're talking about, I have included the assembly > output from two compilations, one with a user explicit catch-all, one with only an > implicit cleanup, the DWARF Action Table and Types Table are absolutely identical, > as are the indexes used to reference the Action Table from
2013 Feb 27
0
[LLVMdev] [PATCH] [Embtk] [compiler-rt] ASAN: Add mips support
On Wed, Feb 27, 2013 at 11:09 PM, Abdoulaye Walsimou Gaye <awg at embtoolkit.org> wrote: > This simple patch makes asan compile for mips (tested on mips32r2el). > The following test code: > int main() > { > char *x = (char*)malloc(10 * sizeof(char*)); > free(x); > return x[5]; > } It would help to enable compiler-rt tests on mips builders to
2013 Feb 27
2
[LLVMdev] [PATCH] [Embtk] [compiler-rt] ASAN: Add mips support
This simple patch makes asan compile for mips (tested on mips32r2el). The following test code: int main() { char *x = (char*)malloc(10 * sizeof(char*)); free(x); return x[5]; } leads to the following output at runtime: ================================================================= ==267== ERROR: AddressSanitizer: heap-use-after-free on address 0x77900fd5 at pc 0x409e1c bp 0x7fb781d8 sp
2013 Mar 18
0
[LLVMdev] Running cross compiled binaries for ARM on gem5
On 18 March 2013 09:43, Abdoulaye Walsimou Gaye <awg at embtoolkit.org> wrote: > ** > This is the same issue reported here > http://llvm.org/bugs/show_bug.cgi?id=15429 > Yes, it does look like the same problem, thanks! Silky, feel free to add your error messages to that bug to make sure it's taken into account when fixed. cheers, --renato -------------- next part
2010 Sep 10
3
[LLVMdev] Cross-compiling the ARM toolchain
On 10 September 2010 04:47, Liu <proljc at gmail.com> wrote: > trying this: > clang -march=armv7-a -mcpu=cortex-a9 -ccc-host-triple > arm-none-linux -ccc-gcc-name arm-none-linux-gnueabi-gcc a.c Hi Liu, That doesn't work for me. $ clang -march=armv7-a -mcpu=cortex-a9 -ccc-host-triple arm-none-linux -ccc-gcc-name arm-none-linux-gnueabi-gcc alias.c clang: warning: unknown
2012 Jul 18
0
[LLVMdev] Setting up a cross-compiler for cortex-m3
On Wed, Jul 18, 2012 at 4:31 PM, Renato Golin <rengolin at systemcall.org> wrote: > On 18 July 2012 15:24, salvatore benedetto > <salvatore.benedetto at gmail.com> wrote: >> I'm not sure how to interpret the above output, but I don't understand >> why if say -triple armv4t-none--gnueabi . > > Ok, we're getting there... ;) Glad you are confident.
2012 Sep 26
0
[LLVMdev] [Questions] clang cross compilation and SimpleScalar simulation
Dear all I use arm-linux-gcc 2.95.2, because the code generated by version 3.X and 4.X can not run on SimpleScalar. So I use the arm-linux-gcc 2.95.2 *only*, the version is recommended by SimpleScalar. The code generated by arm-linux-gcc 2.95.2 can run on SimpleScalar. Now I want to use llvm/clang to generate ARM assembly code and arm-linux-gcc 2.95.2 to be assembler. Unfortunately, I got some
2012 Sep 26
1
[LLVMdev] [Questions] clang cross compilation and SimpleScalar simulation
Simplescalar is not compatible with llvm because the binutils simplescalar is based on is ancient. Jim On Sep 26, 2012, at 12:21 AM, 陳奕梅 <ymchen at sslab.cs.nctu.edu.tw> wrote: > Dear all > > I use arm-linux-gcc 2.95.2, because the code generated by version 3.X and 4.X can not run on SimpleScalar. > So I use the arm-linux-gcc 2.95.2 *only*, the version is recommended by
2014 Dec 19
2
[LLVMdev] questions about ARM EABI attributes
ARM backend emits different eabi build attributes based on the ISA variant the target supports or whether certain fast-math options are passed on the command line. For example, these are the attributes that have different values depending on whether -ffast-math is passed to clang: $ clang -target armv7-linux-gnueabi -ffast-math (with -ffast-math) .eabi_attribute 20, 2 @ Tag_ABI_FP_denormal
2011 Aug 05
3
[LLVMdev] RFC: Exception Handling Rewrite
Bill, ooops, yes, I described the meaning of "throw(A)" backwards, but I still think my example shows why you cannot merge LandingpadInst while inlining because multiple filter-lists on a LandingpadInst don't make sense. Perhaps I'm reading your original spec wrong, perhaps I'm mis-reading Duncan's emails, but I read them to mean that your syntax supports
2016 May 12
3
Why LR is saved before calling a 'noreturn' function ?
Dear all, I don't get how llvm handles functions with __attribute__((noreturn)). It seems that LR register is backed up on the stack whilst it will never be used to return from a 'noreturn' function. I have this problem with a home-made backend but it seems that ARM flavour of clang has same behaviour. By the way, SP is also saved, I don't understand why. Is there a syntax error
2010 Jan 22
0
[LLVMdev] Exception handling question
2010/1/22 James Williams <junk at giantblob.com> > > > 2010/1/22 Duncan Sands <baldrick at free.fr> > > Hi James, >> >> >> I've been trying to get a minimal test function to work, which simply >>> invokes _Unwind_RaiseException with a single clean-up landing pad. However. >>> when I run it my personality function is not getting
2019 Jul 12
2
[cfe-dev] ARM float16 intrinsic test
Hi, I do not get your result. Do I miss something? $COMP_ROOT/clang++ --target=arm-arm-eabihf -march=armv8.2a+fp16 arm.cpp -S -o - -O3 .text .syntax unified .eabi_attribute 67, "2.09" .eabi_attribute 6, 14 .eabi_attribute 7, 65 .eabi_attribute 8, 1 .eabi_attribute 9, 2 .fpu crypto-neon-fp-armv8 .eabi_attribute 12, 4
2010 Jan 22
2
[LLVMdev] Exception handling question
2010/1/22 Duncan Sands <baldrick at free.fr> > Hi James, > > > I've been trying to get a minimal test function to work, which simply >> invokes _Unwind_RaiseException with a single clean-up landing pad. However. >> when I run it my personality function is not getting called - >> _Unwind_RaiseException simply returns apparently doing nothing. Looking at
2010 Jan 22
0
[LLVMdev] Exception handling question
Hi James, > I've been trying to get a minimal test function to work, which simply > invokes _Unwind_RaiseException with a single clean-up landing pad. > However. when I run it my personality function is not getting called - > _Unwind_RaiseException simply returns apparently doing nothing. Looking > at the x86-64 assembly output from llc, I can see this is happening >
2013 Sep 09
2
[LLVMdev] ARM integrated assembler - unknown directive errors
Hiya I am trying to compile a test case with latest LLVM 3.3 release using integrated assembler. I have looked through previous mailing discussion on this subject and it appears that perhaps by now the appropriate changes are checked-in however my test case is failing. Maybe I am missing something and not specifying appropriate options on the commandline. My setup: Host operating System: Ubuntu
2018 Jan 06
2
LLVM EH tables much larger than GCC's
Hi, I'm investigating the size of Clang's generated binaries relative to GCC, when targeting Android, and I've noticed that Clang's exception tables are much larger -- the .ARM.extab section is about 2.5 times as large in two examples. I noticed a couple of differences between Clang and GCC: 1. *ULEB128 encoding.* In the call site table, GCC encodes offsets using a ULEB128
2015 Dec 30
2
Substitute instruction with a jump to a library code
I'm trying to find a way to emulate a floating point instruction, say a floating point add. My understanding is that in order to do that I need to execute setOperationAction(ISD::FADD, (MVT::f32, Expand); setOperationAction(ISD::FADD, (MVT::f64, Expand); in MyTargetISelLowering.cpp, MyTargetLowering::MyTargetLowering(...). However for some reason I'm still seeing a floating point add in
2013 Oct 15
1
[LLVMdev] Unwanted push/pop on Cortex-M.
Hi andrea, R11 treated as frame pointer at arm backend , which is fixed again . Thanks Umesh On Tuesday, October 15, 2013, Andrea Mucignat <andrea at nestlabs.com> wrote: > Umesh, > Makes some sort of sense to me, OTOH: > If instead of choosing r11 as a "dummy" to align the stack we had chosen some other register in the range r0-r7 then we could have emitted the PUSH