similar to: [LLVMdev] ARM interrupt attributes (IRQ and FIQ) support

Amaury, > GCC does, or if there is no plan to support this in future ? I am no llvm > expert but with some help I think I could implement this if it is a wanted > feature. The answer is easy - noone needed them in the past, thus they were not implemented... -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University

Right, later in the same file we have: // Reserve entries in the vector for each of the SUnits we are creating. This // ensure that reallocation of the vector won't happen, so SUnit*'s won't get // invalidated. // FIXME: Multiply by 2 because we may clone nodes during scheduling. // This is a temporary workaround. SUnits.reserve(NumNodes * 2); So for some reason *2 is

Oh yes you're right, I missed that :) But the point still hold. Amaury Pouly 2010/8/8 Eugene Toder <eltoder at gmail.com> > > Not only this code does not compile with NDEBUG set > > I may be missing something, but why does it not compile with -DNDEBUG? > assert() macro expands to noop when NDEBUG is set. > > Eugene > > On Sun, Aug 8, 2010 at 2:19 PM, Amaury

> Not only this code does not compile with NDEBUG set I may be missing something, but why does it not compile with -DNDEBUG? assert() macro expands to noop when NDEBUG is set. Eugene On Sun, Aug 8, 2010 at 2:19 PM, Amaury Pouly <amaury.pouly at gmail.com> wrote: > Hello, > I was trying to interface a custom backend instruction scheduler with llvm > code when I realize

While I'm at it, I noticed a behaviour which is not exactly related but similar. To put it simply, you can 't do T.V.W, you need to do !cast<Bla>(T.V).W Example: class Bla<string t> { string blu = t; } class Bli<Bla t> { Bla bla = t; } def a : Bli<Bla<"">>; def b : Bla<!cast<Bla>(a.bla).blu>; // works def b :

On Sep 1, 2010, at 4:35 AM, Amaury Pouly wrote: > Hello, > I was fiddling with TableGen (for a use that has nothing to do with a compiler but it's doesn't matter) and TableGen triggers an assertion failure on this code (I reduced the case to the minimum, it's a parsing bug): David, can you take a look? This is related to your lisp interpreter :) -Chris > > class

Hello, I was trying to interface a custom backend instruction scheduler with llvm code when I realize something terrible. The scheduling code builds a graph made up of SUnit * nodes (see ScheduleDAG*.{cpp,h}). These SUnits nodes are allocated via a std::vector< SUnit >. This isn't a problem as long as the pointers are taken after the vector is fully filled and the vector never changes

Hello, Still trying to write a custom scheduler, I stumbled accross a highly suspicious code in all schedulers. In both ScheduleDAGFast.cpp and ScheduleDAGRRList.cpp, one can find this piece of code: SUnit *CopyFromSU = CreateNewSUnit(NULL); and then in the same files: SUnit *CreateNewSUnit(SDNode *N) { [...] SUnit *NewNode = NewSUnit(N); And finally in ScheduleDAGSDNodes.cpp: SUnit

Hello, I have recently been working on scheduling for register pressure and ran into the issue of alias analysis when trying to integrate it with LLVM. Looking at the code it seems that the pre register allocation scheduling doesn't use alias analysis information. On the contrary, post-RA uses it. I'm wondering if there is a good reason for this fact. Indeed, it seems to me that alias

Hello, I was fiddling with TableGen (for a use that has nothing to do with a compiler but it's doesn't matter) and TableGen triggers an assertion failure on this code (I reduced the case to the minimum, it's a parsing bug): class Bli<string _t> { string t = _t; } class Bla<list<Bli> _bli> : Bli<!car(_bli).t> { } #0 0x00007ffff6ebda75 in *__GI_raise

Hey ppl ! My WinXP workstations are not able to join my domain. I tried to apply the registry fix for plain-text passwords but it has no effects :( My PDC seems to work fine cause i've got no problems with Win2K Workstations... Is there anything i've omitted ? Regards, Amaury -------------- next part -------------- HTML attachment scrubbed and removed

I'd think i1 would be the proper and correct choice for a carry flag for the generic instruction. I expect that would also make UADDO/USUBO redundant with ADDC/SUBC (which would seem a good outcome). You'd need to make sure the right thing happened when converting from ADDC's 1-bit carry in/out to X86ISD::AD[DC]'s EFLAGS i/o. Right now the conversion can get away with assuming

Explicitly re-adding a node to be processed doesn't work, because the processing order is canonical. 2017-05-22 11:39 GMT-07:00 Nirav Davé <niravd at google.com>: > You can always explicitly add D to the worklist when you make the > transformation with AddToWorklist. Presuambly this was the cause for your > infinite loop. > > -Nirav > > > On Mon, May 22, 2017 at

I don't think that'd work, because it leaves all other backends broken. AFAICT, your transform is simply not a legal transform, with the way the ADDC/ADDE opcodes are currently defined, and to do it you really need to fix the opcode definitions to not involve glue, first. I also note that your transform doesn't actually trigger at all on this particular test case on x86, because the

Most softphnes (like Idefisk and X-Lite) have a phonebook. Is there a way I can fill those phonebooks with info from the Asterisk server? Amaury Rodr?guez http://liberadospucmm.blogspot.com http://groups.msn.com/telematicaPUCMM2002 Go OpenSource And Be FREE!! --------------------------------- Yahoo! Mail Bring photos to life! New PhotoMail makes sharing a breeze.

Would it not make sense to refactor the code so those don't use glue rather than emitting them with glue and then getting rid of it. There are times when we would like to emit these in separate blocks but can't (presumably because of the glue). On Tue, Feb 7, 2017 at 9:15 PM, James Y Knight via llvm-dev < llvm-dev at lists.llvm.org> wrote: > That's seems really odd that

That's a very interesting information. Is there, somewhere, a list of these computed attributes and their meaning? Best regards, mathias 2015-11-26 9:34 GMT+01:00 Andrew Bartlett <abartlet at samba.org>: > On Thu, 2015-11-26 at 00:40 -0500, Amaury Viera Hernández wrote: > > Hi every one: > > I'm using samba4 as domain controller and a I want to check every 1 >

Hi all, I am building an Asterisk PBX with voicemail and music on hold functions. An ISDN BRI line will also be available and G.729 IP-phones will be used. Are there patents rights applicable to France? Which licence could I use and how many ones are required (only one per phone or also for voicemail and MOH)? Regards Amaury -------------- next part -------------- An HTML

On 01/04/2016 07:32 AM, Amaury SECHET wrote: > After a bit more investigation, it turns out that because %0 is stored > into %1 (after bitcast) and so %3 may have access to it and clobber it. Can you give a bit more context? I'm not sure which of the examples you're talking about. > > After a bit of thought, it is correct in the general case, but > definitively something

These opcodes have been deprecated about a year ago, but still in use in various backend. In https://reviews.llvm.org/D47422 I would like to change the behavior of the backend to not enable the use of these opcodes by default. The opcode remains usable by any backend that wish to use them, but that should limit the situation where newer backend just use them as they are enabled by default. This