Displaying 7 results from an estimated 7 matches similar to: "[LLVMdev] Sub-Register Allocation"
2013 Jan 12
0
[LLVMdev] Sub-Register Allocation
On Jan 10, 2013, at 9:54 PM, Kenneth Waters <kwwaters at gmail.com> wrote:
> I have a pattern where I load the 16 bit portion of the register with 0, and then copy in the 8 bit portion.
>
> def : Pat<(i16 (zextloadi8 addr:$src)),
> (INSERT_SUBREG (MOV16id 0), (MOV8md addr:$src), sub_byte)>;
>
> which produces working but odd assembly,
>
>
2019 Sep 10
2
tablegen exponential behavior
Hi,
I implemented a pattern matching of the dot product for arm64
and it seemed to work well for the basic case, i.e.,
class mulB<SDPatternOperator ldop> :
PatFrag<(ops node:$Rn, node:$Rm, node:$offset),
(mul (ldop (add node:$Rn, node:$offset)),
(ldop (add node:$Rm, node:$offset)))>;
class mulBz<SDPatternOperator ldop> :
PatFrag<(ops node:$Rn,
2009 Mar 15
5
[LLVMdev] Overlapping register classes
Hi,
I am writing a backend for the Blackfin processor from Analog Devices. I
just started so I still have a lot to learn about the code generator. So
far, I can compile test/CodeGen/Generic/BasicInstrs.ll correctly, but
that is about it.
The Blackfin 32-bit registers divide naturally into several classes. I
have modelled these register classes without knowing anything about what
the code
2009 Mar 16
0
[LLVMdev] Overlapping register classes
On Mar 15, 2009, at 2:02 PM, Jakob Stoklund Olesen wrote:
> Hi,
>
> I am writing a backend for the Blackfin processor from Analog
> Devices. I
> just started so I still have a lot to learn about the code
> generator. So
> far, I can compile test/CodeGen/Generic/BasicInstrs.ll correctly, but
> that is about it.
>
> The Blackfin 32-bit registers divide naturally
2011 Jun 23
0
[LLVMdev] Instr Description Problem of MCore Backend
Hello
> Finally, I don't know how to describe following instructions in
> MCoreInstrInfo.td, because of its variable ins/outs. Or what other files
> should I use to finish this description?
Do you need the isel support for them? If yes, then you should custom
isel them. iirc ARM and SystemZ backends have similar instructions,
while only the first one supports full isel for them. In
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
Sure I will split it and put it in two patches.
Give me few hours. I need to test those patches.
Sirish
On 4/19/2012 8:40 AM, Tom Stellard wrote:
> On Wed, Apr 18, 2012 at 11:18:05PM -0500, Sirish Pande wrote:
>> Hi,
>>
>> Here's a patch for Hexagon Packetizer for review. This patch does
>> not yield any warnings.
>>
> Would it be possible to split this
2011 Jun 23
2
[LLVMdev] Instr Description Problem of MCore Backend
Hi, all:
Now I'm working on writing a backend for Moto MCore, but I don't know how to
describe some instructions.
First, I've already written MCoreRegisterInfo.td like these:
class MCoreReg<bits<4> num, string name> : Register<name> {
let Namespace = "MCore";
field bits<4> Num = num;
}
def R0 : MCoreReg< 0, "R0">,