Displaying 20 results from an estimated 200 matches similar to: "[LLVMdev] LSR pass"
2012 Dec 01
1
[LLVMdev] LSR pass
----- Original Message -----
> From: "Jonas Paulsson" <jonas.paulsson at ericsson.com>
> To: llvmdev at cs.uiuc.edu
> Sent: Monday, November 26, 2012 1:40:24 PM
> Subject: [LLVMdev] LSR pass
>
>
>
>
>
> Hi,
>
>
>
> I would like some help regarding the LSR pass. It seems that it likes
> to duplicate address calculations as in the
2012 Dec 04
0
[LLVMdev] LSR pass
Hi,
The target supports indexing by register or immediate. Multiplications are not supported by any load / store instructions. Would it be possible to make LSR aware of this?
Thanks,
Jonas Paulsson
-----Original Message-----
From: Hal Finkel [mailto:hfinkel at anl.gov]
Sent: Saturday, December 01, 2012 5:59 AM
To: Jonas Paulsson
Cc: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] LSR pass
2017 Jan 13
4
Wrong code bug after GVN/PRE?
Hi,
I've stumbled upon a case where I think gvn does a bad (wrong)
optimization. It's a bit messy to debug though so I'm not sure if I
should just write a PR about it a let someone who knows the code look at
it instead.
Anyway, for the bug to trigger I need to run the following passes in the
same opt invocation:
-sroa -instcombine -simplifycfg -instcombine -gvn
The problem
2010 Jun 29
0
[LLVMdev] Confuse on getSCEVAtScope
On Jun 29, 2010, at 7:08 AM, ether zhhb wrote:
>
> why computeSCEVAtScope not try to get the operands in the current
> scope like the function do with SCEVCommutativeExpr, like:
>
> if (const SCEVAddRecExpr *AddRec = dyn_cast<SCEVAddRecExpr>(V)) {
> if (!L || !AddRec->getLoop()->contains(L)) {
> ...
> // Then, evaluate the AddRec.
>
2010 Jun 29
2
[LLVMdev] Confuse on getSCEVAtScope
hi all,
i have SCEVAddRec
{{(32 + @edge.8265),+,32}<Loop0>,+,4}<Loop1>
where Loop0 and Loop1 are brothers (loops at the same level of the
loopnest), and Loop0 have a computable backedge taken count.
when i call getSCEVAtScope({{(32 +
@edge.8265),+,32}<Loop0>,+,4}<Loop1> , Loop1), it just give me a
{{(32 + @edge.8265),+,32}<Loop0>,+,4}<Loop1>,
instead of
2011 Jul 07
1
[LLVMdev] code generation removes duplicated instructions
Ok. Let me describe the problem again in some detail.
The following is the original bitcode from a real testcase:
bb7:
%46 = load i32* %j, align 4
%47 = add nsw i32 %46, 1
store i32 %47, i32* %j, align 4
br label %bb8
To protect the operand of the store I duplicate the input chain of operands
and insert a comparison to check whether the operand of the stores are
correct. As a result of
2010 May 08
2
[LLVMdev] Remove identical or redundant basic blocks?
Dear all,
after optimizing a small LLVM example program (i.e., with opt -O3), the
resulting code contains several basic blocks, which I consider identical
or redundant. For instance,
return: ; preds = %min.exit
ret i32 0
bb15: ; preds = %min.exit
ret i32 0
or,
bb7.i:
2011 Jul 07
0
[LLVMdev] code generation removes duplicated instructions
On 7 July 2011 00:02, D S Khudia <daya.khudia at gmail.com> wrote:
> I am trying to add a intrinsic call between the similar two instructions
> which either I'll remove or convert to nopĀ in codegen.
If the two instructions are only similar in your real example, than
you need to make them similar in your test, not identical. Different
offsets, different array...
If them two are
2011 Jul 06
2
[LLVMdev] code generation removes duplicated instructions
Hi Renato,
I am trying to add a intrinsic call between the similar two instructions
which either I'll remove or convert to nop in codegen.
Does that kind of seem appropriate for the purpose here?
Thanks
Daya
On Wed, Jul 6, 2011 at 11:55 AM, Renato Golin <renato.golin at arm.com> wrote:
> On 6 July 2011 15:57, D S Khudia <daya.khudia at gmail.com> wrote:
> > Since I am
2010 May 08
2
[LLVMdev] Remove identical or redundant basic blocks?
Would it make sense to have a similar pass that operates on llvm main IR?
On Sat, May 8, 2010 at 5:15 PM, Dale Johannesen <dalej at apple.com> wrote:
> The branch folding pass does this, but it operates later, on the
> target-dependent form in llc.
>
> On May 8, 2010, at 8:48 AM, Heinz Riener wrote:
>
>> Dear all,
>>
>> after optimizing a small LLVM example
2010 May 08
0
[LLVMdev] Remove identical or redundant basic blocks?
The branch folding pass does this, but it operates later, on the
target-dependent form in llc.
On May 8, 2010, at 8:48 AM, Heinz Riener wrote:
> Dear all,
>
> after optimizing a small LLVM example program (i.e., with opt -O3),
> the
> resulting code contains several basic blocks, which I consider
> identical
> or redundant. For instance,
>
> return:
2007 Feb 05
1
[LLVMdev] Misc optimization issue
This is from 'early JIT tests' thread on comp.lang.misc.
Given :-
int ltst(int x)
{
int i, j;
j=0;
for(i=0; i<x; i++)j++;
return(j);
}
This is from the online LLVM compiler. AND It does not seem to optimize it down !
; ModuleID = '/tmp/webcompile/_24843_0.bc'
target datalayout = "e-p:32:32"
target endian = little
target pointersize = 32
target triple =
2010 May 09
0
[LLVMdev] Remove identical or redundant basic blocks?
Eugene Toder wrote:
> Would it make sense to have a similar pass that operates on llvm main IR?
>
The unify exit return node (-mergereturn?) pass should take care of the
first example. The -simplifycfg option might take care of the second
example. Both work on LLVM IR.
-- John T.
> On Sat, May 8, 2010 at 5:15 PM, Dale Johannesen <dalej at apple.com> wrote:
>
>>
2011 Nov 21
1
[LLVMdev] Fwd: Order of Basic Blocks
---------- Forwarded message ----------
From: Ryan Taylor <ryta1203 at gmail.com>
Date: Mon, Nov 21, 2011 at 10:30 AM
Subject: Re: [LLVMdev] Order of Basic Blocks
To: Benjamin Kramer <benny.kra at googlemail.com>
This worked, though the RPO_iterator apparently wasn't what I was looking
for anyways, it seems it doesn't rreally go top->down.
I have a simple example code,
2009 Sep 13
2
[LLVMdev] PIC16 question
In my ongoing work on refactoring the asmprinters, I've found that
PIC16 doesn't put ':' after labels in some cases. Specifically, it
looks like basic block labels are emitted without a ':':
movwf @__floatunsidf.frame. + 2
movlp .BB1_2
goto .BB1_2
.BB1_2 ; %bb7
movlw 0
banksel @__floatunsidf.frame.
but that
2016 Feb 08
2
LoopIdiomRegognize vs Preserved
Hi,
I'm having problems with the LoopIdiomRegognizer crashing on me with
An asserting value handle still pointed to this value!
UNREACHABLE executed at ../lib/IR/Value.cpp:695!
If I remove
AU.addPreserved<LoopInfoWrapperPass>();
or
AU.addPreserved<AAResultsWrapperPass>();
everything goes well.
The C-code triggering this is
void foo(int a[10][10])
{
int i, j,
2014 Jan 20
1
ISDN Cause Code 47 Errors
We fairly recently switched service providers for our 4 PRI circuits. Since
that time, we started to notice some failed inbound calls. These calls
terminate with an ISDN cause code 47 'resource unavailble'. Most of the
time I see this error on the first or second channel on the second span in
a trunk group (This is the providers trunk group for hunting, not an
Asterisk trunk group). All
2010 Aug 05
3
[LLVMdev] a problem when using postDominatorTree
On 08/05/2010 06:46 AM, Wenbin Zhang wrote:
> Hi all,
> I'm using postDominatorTree to do some program analysis. My code works
> well for small tests, but when I run it on real applications, the
> following error occurs:
> /Inorder PostDominator Tree: DFSNumbers invalid: 0 slow queries.
> [1] <<exit node>> {0,21}
> [2] %bb1 {1,2}
> [2] %bb {3,4}
> [2]
2009 Sep 03
2
[LLVMdev] Non-local DSE optimization
Hi,
It looks like PDT.getRootNode() returns NULL for:
define fastcc void @c974001__lengthy_calculation.
1736(%struct.FRAME.c974001* nocapture %CHAIN.185) noreturn {
entry:
br label %bb
bb:
br label %bb
}
Isn't it a bug in PostDominatorTree?
Please note that this crashes:
opt -postdomtree -debug dom_crash.bc
I think this should be reported as a bug,
-Jakub
On Sep 3, 2009, at
2009 Sep 03
0
[LLVMdev] Non-local DSE optimization
Hi Jakub, interesting patch. I ran it over the Ada testsuite and this
picked up some problems even without enabling dse-ssu. For example,
"opt -inline -dse -domtree" crashes on the attached testcase.
Ciao,
Duncan.
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