similar to: [LLVMdev] Is there a stubbed out target definition available somewhere?

> However, figuring out what can and cannot be deleted from the sparc backend > while still compiling is proving rather frustrating. Why are you looking into sparc backend? I believe the talk makes clear which backend should be considered as a start point (at that time). In any case, https://github.com/asl/llvm-openrisc is better "stub" backend, at least it's 'just' 6

On 24 September 2013 03:00, Sean Silva <chisophugis at gmail.com> wrote: > http://llvm.org/devmtg/2009-10/Korobeynikov_BackendTutorial.pdf > He did this again last year at the EuroLLVM: http://llvm.org/devmtg/2012-04-12/Slides/Workshops/Anton_Korobeynikov.pdf They're similar, but different. I assume the newer one is better, but you can look at both, shouldn't take too long.

> Maybe this would make a good GSOC project. It's definitely too small project for a GSoC. One can try to start from https://github.com/asl/llvm-openrisc (openrisc branch inside), however, it's already 2 years old... -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State Universit

I'm trying to port LLVM to a new architecture. I'm finding that the initial bootstrapping stage of getting something which will build, even if it doesn't work, is complex and rather disheartening --- there's this huge cliff of difficulty in just getting all the boilerplate laid out correctly, before getting to the fun stuff. The other backends are of limited use here because, of

> http://llvm.org/devmtg/2012-04-12/Slides/Workshops/Anton_Korobeynikov.pdf > > They're similar, but different. I assume the newer one is better, but you > can look at both, shouldn't take too long. Yeah, right. The EuroLLVM one was a "refreshed" version of the first one. For example, there was no MC in 2009 and so on. The backend stub is available at

Hi, I'm working on a project that use llvm openrisc beckend (currently not part of the upstream). Right now I'm looking at a bug where llc generates memory instructions that has out-of-range displacement, for example l.sb 37668(r1), r2 in which 37668 is a 17 bit signed integer, but the instruction only allows 16 bit signed displacement. As a result, after running through the

Hi, While crosscompiling the kernel for openrisc with allmodconfig the build failed with the error: drivers/vhost/vhost.c: In function 'vhost_vring_ioctl': drivers/vhost/vhost.c:818:3: error: call to '__compiletime_assert_818' declared with attribute error: BUILD_BUG_ON failed: __alignof__ *vq->avail > VRING_AVAIL_ALIGN_SIZE Can you please give me any idea about what the

Hi, While crosscompiling the kernel for openrisc with allmodconfig the build failed with the error: drivers/vhost/vhost.c: In function 'vhost_vring_ioctl': drivers/vhost/vhost.c:818:3: error: call to '__compiletime_assert_818' declared with attribute error: BUILD_BUG_ON failed: __alignof__ *vq->avail > VRING_AVAIL_ALIGN_SIZE Can you please give me any idea about what the

No need to duplicate the same define everywhere. Since the only user is stop-machine and the only provider is s390, we can use a default implementation of cpu_relax_yield in sched.h. Suggested-by: Russell King <linux at armlinux.org.uk> Signed-off-by: Christian Borntraeger <borntraeger at de.ibm.com> --- arch/alpha/include/asm/processor.h | 1 - arch/arc/include/asm/processor.h

No need to duplicate the same define everywhere. Since the only user is stop-machine and the only provider is s390, we can use a default implementation of cpu_relax_yield in sched.h. Suggested-by: Russell King <linux at armlinux.org.uk> Signed-off-by: Christian Borntraeger <borntraeger at de.ibm.com> --- arch/alpha/include/asm/processor.h | 1 - arch/arc/include/asm/processor.h

Hi Everyone, I have been implementing the integrated assembler for the OpenRISC 1000 architecture. Whilst doing this I noticed a lack of documentation around this area. To help others, I have written a how to guide which uses the OpenRISC 1000 as an example. This can be downloaded from http://www.embecosm.com/download/ean10.html. I hope this document proves useful. Any feedback would be

Who is a code owner for MSP430 target? I know that a lot of work on this target is done by Anton Korobeynikov (aka asl) but he is not listed as a code owner in CODE_OWNERS.TXT. I would like to get my D20162 reviewed, but I don't know who I can add as a reviewer.

Dear All, I am trying to custom lower 32-bit ISD::SHL and SHR in a backend for 6502 family CPUs. The particular subtarget has 16-bit registers at most, so a 32-bit result is not legal. Normally, if you mark this as "Legal" or "Expand", then it will expand the node into a more nodes as follows in an example: shl i32 %a , 2 => high_sdvalue = (or (shr %b, 14), (shl %c, 2) )

I had a similar problem with a backend for the 68HC12 family which also has no barrel shifter. Some 68HC12 CPUs support shift for just one of the 16-bit registers and only support rotation on the 2 8-bit subregs of that 16-bit register. That means the only practical solution for 32-bit shifts is to lower to a libcall but my situation for 16-bit shifts sounds similar to yours for 32-bit shifts. I

I forgot to mention that I used EXTRACT_ELEMENT in my backend to get the high and low parts of an SDValue. On 10 Nov 2013, at 17:50, Steve Montgomery <stephen.montgomery3 at btinternet.com> wrote: > I had a similar problem with a backend for the 68HC12 family which also has no barrel shifter. Some 68HC12 CPUs support shift for just one of the 16-bit registers and only support rotation

Wow this is awesome! Would it be okay if we linked to this from llvm.org/docs? -- Sean Silva On Tue, Oct 16, 2012 at 5:55 PM, Simon Cook <simon.cook at embecosm.com> wrote: > Hi Everyone, > > I have been implementing the integrated assembler for the OpenRISC 1000 > architecture. > > Whilst doing this I noticed a lack of documentation around this area. To > help others,

Yes, please do. Simon On Wed 17 Oct 2012 02:20:17 BST, Sean Silva wrote: > Wow this is awesome! Would it be okay if we linked to this from llvm.org/docs? > > -- Sean Silva > > On Tue, Oct 16, 2012 at 5:55 PM, Simon Cook <simon.cook at embecosm.com> wrote: >> Hi Everyone, >> >> I have been implementing the integrated assembler for the OpenRISC 1000 >>

Please CC me. I will review. On Mon, May 23, 2016 at 2:46 PM, Vadzim Dambrouski via llvm-dev <llvm-dev at lists.llvm.org> wrote: > Who is a code owner for MSP430 target? I know that a lot of work on this target is done by Anton Korobeynikov (aka asl) but he is not listed as a code owner in CODE_OWNERS.TXT. I would like to get my D20162 reviewed, but I don't know who I can add as a

Thank you. I don't know what CC means, but I will ping the diff so you can get an email. > On May 23, 2016, at 15:06, Anton Korobeynikov <anton at korobeynikov.info> wrote: > > Please CC me. I will review. > > On Mon, May 23, 2016 at 2:46 PM, Vadzim Dambrouski via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> Who is a code owner for MSP430 target? I

Hi Steve, Thanks for confirming that EXTRACT_ELEMENT is something I can use. I had seen it in the generated DAGs but was unsure whether I was "allowed" to use it, if that's the right word. I checked up on it more and indeed the mainstream targets like ARM use that node type in custom lowering code, so that should solve that. Perhaps in the future I might submit a patch for