similar to: [LLVMdev] tablegen and ptr_rc: PointerLikeRegClass

On Fri, 2012-09-14 at 13:10 -0500, Will Schmidt wrote: > Hi all, > > I've been poking at AsmParser support for powerpc64 > (ppc64-elf-linux-abi) and have run into some behavior I don't understand > with the ptr_rc references coming out of the PPC*.td files when > generating the asm-matcher files. > > For instance : > $ ./build/bin/llvm-tblgen

On Wed, 2012-09-19 at 18:41 -0500, Will Schmidt wrote: > On Fri, 2012-09-14 at 13:10 -0500, Will Schmidt wrote: > > Hi all, > > > > I've been poking at AsmParser support for powerpc64 > > (ppc64-elf-linux-abi) and have run into some behavior I don't understand > > with the ptr_rc references coming out of the PPC*.td files when > > generating the

On Nov 15, 2012, at 2:54 PM, Will Schmidt <will_schmidt at vnet.ibm.com> wrote: > > Can anyone confirm or deny tablegen supporting PointerLikeRegClass? X86 is using it. You could start by determining what PPC is doing differently. /jakob

Hi, Using trunk llvm ; on powerpc (powerpc64/power7); trying to do a "gmake check", the sed bits in test/Makefile appear to be getting tripped up when trying to generate lit.site.cfg. I've started to hack at it, made a little bit of progress, but wonder if I'm just digging myself a hole. Highlights of what I've poked at are below.. Comments or thoughts? Thanks,

Hello, I am having some trouble matching patterns in targetinstructioninfo.td file with the CodeGen expectation. Could anybody please help? Here is the example: I want to emit instruction for adding 2 different kind of oprands. Basically i want to mix register types when I define the instruction for add,sub etc I define the instruction TargetInstruction.td as follows: class MyInst <opcode

Morning, Will! 2012/7/12 Will Schmidt <will_schmidt at vnet.ibm.com>: > llvm]$ gmake check > llvm[0]: Running test suite > gmake[1]: Entering directory `/home/willschm/llvm/test' > Making LLVM 'lit.site.cfg' file... > sed: file lit.tmp line 8: unknown option to `s' > gmake[1]: *** [lit.site.cfg] Error 1 > > The relevant lines in test/Makefile: >

What does MIOperandInfo exactly mean while defining an Operand class? e.g. here class X86MemOperand<string printMethod> : Operand<iPTR> { let PrintMethod = printMethod; let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm); } -------------- next part -------------- An HTML attachment was scrubbed... URL:

On 7 April 2013 14:54, Sam Parker <S.Parker3 at lboro.ac.uk> wrote: > Hi Anitha, > > memri is just describing that the address contains two components, an > immediate and a register, and how to handle them in the instruction printer. > The STWU expects a memri operand, and that is what is passed from the Pat. > My confusion is how operands of STWU from "Pat

On Sun, 28 May 2017, David Chisnall wrote: >> let Constraints = "@earlyclobber $reg" in >> def LDWRdPtr : Pseudo<(outs DREGS:$reg), >> (ins PTRREGS:$ptrreg), >> "ldw\t$reg, $ptrreg", >> [(set i16:$reg, (load i16:$ptrreg))]>, >>

Hi! I'm writing a new back-end for a new architecture. First, I'll do some "tests" with an existing back-end (I chose the Sparc back-end). My architecture has special address-registers and I want to add such new address-registers to my Sparc back-end. 1) I defined a new register call AddrRegs 2) I registered the class AddrRegs (addRegisterClass(MVT::iPTR, .. )) 3) I

Hi, I want to encode Loongson ISA initially https://gist.github.com/xiangzhai/8ae6966e2f02a94e180dd16ff1cd60ac gslbx           $2,0($3,$4) It is equivalent to: dadd $1, $3, $4 lb $2,0($1) I just use  mem_simmptr  as the default value of  DAGOperand MO , because  MipsMemAsmOperand  use  parseMemOperand  to parse general  MemOffset  and only *one*  AnyRegister , for example: 0($1) But 

Hello, I'm trying to define in my new back end, in MyBackendInstrInfo.td file, a vector load instruction that takes an immediate address operand. (I got inspired from Mips' MSA SIMD extensions.) Could you please tell me what's the right way to do it? Here, the load class has $addrsrc which is a relative address with base a certain register and offset: class

On Sep 24, 2007, at 1:12 AM, Andreas Fredriksson wrote: > On 9/24/07, Evan Cheng <evan.cheng at apple.com> wrote: > >> I am going to suggest something shocking. :) Since you will end up >> writing a >> bunch of target specific code anyway, you might a well write a target >> specific pass that change generic instructions into data register >> variant

On Tue Aug 04 20:56:18 +0200 2009, Rafael Espindola wrote: > >    git clone git://github.com/earl/llvm-mirror.git llvm > >    cd llvm > >    git config --add remote.origin.fetch '+refs/remotes/*:refs/remotes/*' > >    git fetch > >    git svn init https://llvm.org/svn/llvm-project/llvm/trunk > >    git svn rebase --local > > This one worked

Greetings! We are running an rsync process every hour and it is producing a core file. We thought initially there was a corrupt file but that is gone and the core file is still being produced. Would appreciate any help in analysing the core file. Thanks, Vincent Soosai Java Developer Phone: 503 745 2615 If you are not the intended addressee, please inform us immediately that you have

On Tue, 30 May 2017, Nemanja Ivanovic wrote: > This is typically accomplished with something like PPC's `RegConstraint` and > `NoEncode`. You can see examples of it that are very similar to what you're after in > PPC's load/store with update forms (i.e. load a value and update the base register > with the effective address - these are used for pre-increment loads/stores).

>    git clone git://github.com/earl/llvm-mirror.git llvm >    cd llvm >    git config --add remote.origin.fetch '+refs/remotes/*:refs/remotes/*' >    git fetch >    git svn init https://llvm.org/svn/llvm-project/llvm/trunk >    git svn rebase --local This one worked perfectly. Thanks! I tried the same with the llvm-gcc-4.2 mirror, but "git svn rebase --local"

On 9/25/07, Evan Cheng <evan.cheng at apple.com> wrote: > > Hi Evan, > > wouldn't this generate fairly terrible code if each address register > > use has to be preceded by instructions to make an address register > > hold the right value? > > No. I would suggest doing this as a instruction selection post pass. > It would operate on DAGs so you still get

A call to drm_simple_encoder_init() initializes an encoder without further functionality. It only provides the destroy callback to cleanup the encoder's state. Only few drivers implement more sophisticated encoders than that. Most drivers implement such a simple encoder and can use drm_simple_encoder_init() instead. The patchset converts drivers where the encoder's instance is embedded in

A call to drm_simple_encoder_init() initializes an encoder without further functionality. It only provides the destroy callback to cleanup the encoder's state. Only few drivers implement more sophisticated encoders than that. Most drivers implement such a simple encoder and can use drm_simple_encoder_init() instead. The patchset converts drivers where the encoder's instance is embedded in