similar to: [LLVMdev] mips 16 port available

> For those doing new ports, you might be interested to study how I did the td > files for mips16. There is still some cleanup I will do but essentially I > have cleanly layered the abstraction into four layers: > 1) machine formats > 2) assembly syntax > 3) instructions (none with patterns) > 4) patterns. Maybe you could write a bit more in-depth about this?

On 01/21/2013 03:28 PM, Sean Silva wrote: > Please add this to <http://llvm.org/docs/CompilerWriterInfo.html> > (docs/CompilerWriterInfo.rst) > > -- Sean Silva I will. I owe a very long mips16 write up , especially for floating point when I'm done. It's very complicated the way they implemented hard float in gcc and it is not documented. It took me some thinking and

When a mips16 wants to return a floating point value, it's at a quandary in mixed mode programs (having both mips16 and mips32 code). float foo() { return 1.0; } Mips16 code is compiled in soft float, with there being an options to have the emulation library be written in mips32 and use floating point instructions in those mips32 support functions (if the machine supports floating

On Mon, Jan 7, 2013 at 4:16 PM, reed kotler <rkotler at mips.com> wrote: > On 01/04/2013 07:45 PM, Eli Friedman wrote: >> >> On Fri, Jan 4, 2013 at 6:28 PM, reed kotler <rkotler at mips.com> wrote: >>> >>> On 01/04/2013 06:08 PM, Eli Friedman wrote: >>>> >>>> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com>

On 01/04/2013 07:45 PM, Eli Friedman wrote: > On Fri, Jan 4, 2013 at 6:28 PM, reed kotler <rkotler at mips.com> wrote: >> On 01/04/2013 06:08 PM, Eli Friedman wrote: >>> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com> wrote: >>>> I'm working on mips16 hard float which at a first approximation is just >>>> soft

On Fri, Jan 20, 2012 at 1:59 PM, reed kotler <rkotler at mips.com> wrote: > We are starting to look at the mips16 and micro mips ports. > > There are various design issues that people may have some good input on. > Especially in how to structure the TD files and other optimizer issues. > > Mips16 is sort of like thumb and Micro Mips like thumb2 as far as I > understand.

We are starting to look at the mips16 and micro mips ports. There are various design issues that people may have some good input on. Especially in how to structure the TD files and other optimizer issues. Mips16 is sort of like thumb and Micro Mips like thumb2 as far as I understand. Mips16 or Micro Mips can live inside of either MIPS32 or MIPS64. In gcc, it's possible using attributes to

Hi Bob, This has turned out to be what appears to be a very obscure binutils bug. I'm working on a test case for it now. I have a patch for Mips16 llvm which works around the issue for now. In general, pure risc architectures have no pity for compiler and toolchain developers. Mips16 is way more extreme in this way than mips32. In mips32, there is no PC register or PC relative

I have some test scripts I use for testing floating point interoperability between mips16 and mips32. There are lots of combinations and there are subtle issues that make them slightly different and they need to all be tested. For a very basic test, I have a program which has a sample function of all floating point signatures that are effected by this. Basically an ABI test for this. This

mips16 has some unusual requirements for label symbols in .s. I think that arm thumb has the same issue but have not located yet how this is handled. When you have a label of an instruction in mips16, when you reference the label, the linker adds a 1 to the address. When you call an odd numbered address, the procesor switches to mips16 mode and when you call an even numbered address it

On Fri, Jan 4, 2013 at 6:28 PM, reed kotler <rkotler at mips.com> wrote: > On 01/04/2013 06:08 PM, Eli Friedman wrote: >> >> On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com> wrote: >>> >>> I'm working on mips16 hard float which at a first approximation is just >>> soft >>> float but calls different library

On 01/04/2013 06:08 PM, Eli Friedman wrote: > On Fri, Jan 4, 2013 at 4:08 PM, reed kotler <rkotler at mips.com> wrote: >> I'm working on mips16 hard float which at a first approximation is just soft >> float but calls different library routines. Those different library routines >> are just an implementation (in mips32 mode) of soft float using mips32 >>

Is it possible to assign the value of subtarget features using more complex expressions with code as opposed to using the mechanism that tablegen affords. For example, if Mips16 or Micro Mips is not present, then I want the subfeature "standard encoding". If I can't do this, then it requires me to write a more complex expression for the "standard encoding" expresions.

Yes, you could have mips16 and fastcc. Mips16 just means that processor mode to execute that function is "mips16". So in a mips16 designated function, I will just emit mips16 instructions and in a "nomips16" function, just emit normal mips32 instructions. I tend to call this "mips32" normal mode, "standard encoding" because in reality the processor is

On 04/24/2013 03:47 PM, Rafael Espíndola wrote: > On 24 April 2013 18:30, reed kotler <rkotler at mips.com> wrote: >> There are a lot of issues. >> >> For one, the function I'm compiling is a mips16 function but the stubs being >> created are mips32 functions. >> > This looks similar to thumb x 32 bit arm. Wouldn't a similar solution > work for

I'm working on the mips16. Mips16 is a mode of the Mips32 (or Mips64) processor. For the most part, it is a compressed form of the MIPS32 instruction set, though not all instructions are supported. Most of the same opcodes and formats are present though sometimes with some restriction. (The micro mips architecture is a true 16 bit compressed form of MIps32 though also with some

What I am thinking of now is to just register the MIPS116 and MIPS32 DAGToDAGISel passes and then within run on machine function, I can just return if the current mode indicates that mips16 is needed for example, so the run on machine function for Mips32 would return immediately. On 03/27/2013 10:05 AM, Reed Kotler wrote: > I guess another way to do this is to just register both passes for

On 24 April 2013 18:30, reed kotler <rkotler at mips.com> wrote: > There are a lot of issues. > > For one, the function I'm compiling is a mips16 function but the stubs being > created are mips32 functions. > This looks similar to thumb x 32 bit arm. Wouldn't a similar solution work for it? Cheers, Rafael

I ran into a case in Mips16 where I need two registers. The problem arises from the fact that SP is not a mips16 register. You can implicitly use it in load/store and, move it to/from a mips16 register and add small immediate values to it but that's it. It's not in general a problem for me because there are a bunch of mips32 registers that are hard to use in mips16 so at this time, I

This seems to work okay. I register both the Mips16 and non Mips16 passes of the instruction selector and then those return false if they are not supposed to be running. Make-check at least passes in this case. So in principle turn on the dual mode now and debug whatever misc is left. For this I insert another pass before the mips16 and non mips16 passes. On 03/27/2013 10:19 AM, Reed Kotler