Displaying 20 results from an estimated 300 matches similar to: "[LLVMdev] Properly handling mem-loc arguments when prologue adjusts FP."
2016 Feb 01
2
TableGen customized node with mayStore attribute is deleted if there is no use
Hi,
I define a customized node with customized type. The job of this customized
node is to move a value from one register class to another class. I find
that if there is no use of the destination register, this node will be
deleted from SDAG. For some reasons, I want to keep this node. So I attach
mayStore attribute to this node and I hope it will not be deleted. However,
it does not work like I
2013 Feb 02
0
[LLVMdev] Moving return value registers from MRI to return instructions
MachineRegisterInfo is maintaining a list of live-out registers for the MachineFunction. It contains the return value registers, and is typically created by XXXISelLowering::LowerReturn().
Various passes after instruction selection need to look at this list to determine which physical registers are live in return blocks. Eventually, the register allocators copy these live-out registers onto the
2015 Nov 25
2
need help for customized backend LowerFormalArguments
Hi, All,
I'm trying to build a customized backend and I need to lower the formal
arguments like this:
There are several specific registers just for storing formal arguments. And
also there are several general purpose registers for computation. If there
is an instruction which uses parameters, I should first use a move
instruction, which moves the value to general purpose register. For
2013 Jun 19
2
[LLVMdev] ARM struct byval size > 64 triggers failure
I missed that the testing case is returning a struct.
You are right in VARegSaveSize.
For callee:
sub sp, sp, #16
push {r11, lr}
mov r11, sp
sub sp, sp, #8
str r3, [r11, #20]
str r2, [r11, #16]
str r1, [r11, #12]
ldr r1, [r11, #76]
The beginning of the input struct @ sp_at_entry - 16 - 8 + 12 = sp_at_entry -12
# of leftover bytes 67-12 = 55
r11+76 is @ sp_at_entry - 24 + 76 = sp_at_entry
2007 Oct 04
3
[LLVMdev] RFC: Tail call optimization X86
Comments:
CheckDAGForTailCallsAndFixThem -
1.
for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
+ BI = prior(DAG.allnodes_end()); BI != BE; BI--) {
Please use pre-decrement instead of post-decrement.
2. The function is slower than it should be. You are scanning all the
nodes in the DAG twice. You should just examine DAG.getRoot() to make
determine whether it's a
2013 Feb 20
1
[LLVMdev] Question about accessing coprocesser register in prologue
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2013 Jun 18
0
[LLVMdev] ARM struct byval size > 64 triggers failure
Hi Rajesh,
The callee code looks okay to me
> Assembly for check114
> ---------------------------------------------------------------
> sub sp, sp, #16
> push {r11, lr}
> mov r11, sp
> sub sp, sp, #8
> str r3, [r11, #20]
> str r2, [r11, #16]
> str r1, [r11, #12]
> ldr r1,
2008 Jan 08
1
[LLVMdev] RFC: Tailcall Improvement
Here is a patch to improve argument lowering for tail calls. Before
this patch all outgoing arguments were move to the stack slot where
they would go on a normal function call and from there moved back to
the tail call stack slot to prevent overwriting of values.
After this patch only arguments that source from callers arguments
(formal_arguments) are lowered this way.
I moved some code
2013 Jun 18
3
[LLVMdev] ARM struct byval size > 64 triggers failure
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2013 Jun 20
1
[LLVMdev] ARM struct byval size > 64 triggers failure
> - "since ABI says the stack pointer needs to be 8 byte aligned at function entry point" (taken from Manman's reply)
> What will be considered as entry point here?
> Is it place of SP Adjustments "sub sp, sp, #16"
> (Or) Is it place of first user instruction(end of prologue) "ldr r2, .LCPI0_0"
Eight byte stack alignment is a
2007 Sep 11
0
[LLVMdev] RFC: Tail call optimization X86
Hi Arnold,
Thanks for the patch. Some questions and commons:
1. Have you test it against the llvm test suite? Does it work if fp
elimination optimization is turned off?
2. Please follow llvm coding convention and make sure every line fits
in 80 columns.
3.
enum NameDecorationStyle {
None,
StdCall,
- FastCall
+ FastCall,
+ FastCC // the normal fastcc calling convention
};
Why is
2007 Oct 02
0
[LLVMdev] RFC: Tail call optimization X86
Hi all,
I changed the code that checks whether a tail call is really eligible
for optimization so that it performs the check/fix in
SelectionDAGISel.cpp:BuildSelectionDAG() as suggest by Evan. Also
eliminated an error that caused the remaining failing test cases in
the test-suite.
The results look very nice (on darwin x86, r42486).
The same number (46) of failing test cases on patched
2017 Apr 27
4
-msave-args backend support for x86_64
ola,
ive been looking at adding support for an -msave-args option for
use on x86_64. the short explanation of it is that it makes x86_64
function prologues store their register arguments on the stack. the
purpose of this is to make the arguments trivially accessible for
things like stack traces with arguments.
as per
https://blogs.oracle.com/sherrym/entry/obtaining_function_arguments_on_amd64,
2007 Sep 26
3
[LLVMdev] RFC: Tail call optimization X86
On Tue, 25 Sep 2007, Evan Cheng wrote:
>> the stack adjustment only fastcc was not one of them. Now that fastcc
>> can cause tail call optimization i had to change the convention from
>> caller pops arguments to callee pops arguments in order to allow tail
>> call optimization in a general way.
>
> Hmmm. Ok. So this is due to X86CallingConv.td changes? Unfortunately
2007 Sep 06
2
[LLVMdev] RFC: Tail call optimization X86
Hi Evan,
first off thanks to you and Chris for taking time.
On 6 Sep 2007, at 00:57, Evan Cheng wrote:
> We'd like to see tail call optimization to be similar to the target
> independent lowering of ISD::CALL nodes. These are auto-generated
> from ???CallingConv.td files. Some target specific details such as
> function address register (ECX in your example) should be coded in
2013 Dec 11
0
[LLVMdev] Switching to the new MingW ABI
Maybe we should also change the stack probing code. I think ___chkstk_ms
is used since gcc 4.6. It simplifies the prologue generation code a bit.
Regards,
Kai
On 10.12.2013 02:18, Rafael EspĂndola wrote:
> Mingw switched abis with the release of gcc 4.7
> (http://gcc.gnu.org/gcc-4.7/changes.html). The main change is that now
> mingw (like msvc) given thiscall calling convention to
2007 Sep 11
2
[LLVMdev] RFC: Tail call optimization X86
Begin forwarded message:
> From: Evan Cheng <evan.cheng at apple.com>
> Date: 11 September 2007 19:26:39 GMT+02:00
> To: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu>
> Subject: Re: [LLVMdev] RFC: Tail call optimization X86
> Reply-To: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu>
>
> Hi Arnold,
>
> Thanks for the patch. Some questions
2012 Nov 26
2
[LLVMdev] RFC: change BoundsChecking.cpp to use address-based tests
I am investigating changing BoundsChecking to use address-based rather
than size- & offset-based tests.
To explain, here is a short code sample cribbed from one of the tests:
%mem = tail call i8* @calloc(i64 1, i64 %elements)
%memobj = bitcast i8* %mem to i64*
%ptr = getelementptr inbounds i64* %memobj, i64 %index
%4 = load i64* %ptr, align 8
Currently, the IR for bounds checking
2012 Nov 26
0
[LLVMdev] RFC: change BoundsChecking.cpp to use address-based tests
Hi Kevin,
Thanks for your interest and for your deep analysis.
Unfortunately, your approach doesn't catch all bugs and is vulnerable to an
attack.
Consider the following case:
...................... | ----- obj --- | |
end ^ ptr ^ ^ end-of-memory
The scenario is as follows:
- an object is allocated in the last page of the address space
- obj is byte
2013 Feb 27
4
[LLVMdev] Question about intrinsic function llvm.objectsize
On Feb 27, 2013, at 4:05 AM, Nuno Lopes <nunoplopes at sapo.pt> wrote:
> Hi,
>
> Regarding the definition of object for @llvm.objectsize, it is identical to gcc's __builtin_object_size(). So it's not wrong; it's just the way it was defined to be.
>
> Regarding the BasicAA's usage of these functions, I'm unsure. It seems to me that isObjectSmallerThan()