Displaying 20 results from an estimated 90 matches similar to: "[LLVMdev] Alternate instruction encoding for subtargets"
2012 Nov 02
0
[LLVMdev] Alternate instruction encoding for subtargets - SOLVED
>> Can I tell tablegen to have two encodings and switch between them
>> using a predicate?
After some deliberations, I modified tablegen to generate several
versions of the GenCodeEmitter file. My tablegen now accepts a new
command line parameter called "emitter-instfld". This specifies the
name of the field in Instruction that holds the encoded bytes. In my
target's td
2011 Nov 09
1
[LLVMdev] Inserting stack spilling code that modifies globally visible state
Hello,
I am developing compiler for the 8-bit PicoBlaze processor in LLVM 2.9.
The problem at hand is that the stack spilling code in this
architecture modifies the machine FLAGS register (i.e. globally
visible state). The LLVM core code does not know about this 'feature'
and happily inserts spilling code anywhere it wants, thus
(potentially) corrupting live FLAGS.
Practically, the FLAGS
2007 Apr 18
2
[LLVMdev] CodeEmitterGen
On Apr 18, 2007, at 2:07 PM, Evan Cheng wrote:
>
> On Apr 18, 2007, at 11:25 AM, Christopher Lamb wrote:
>
>> I noticed that the TableGen code emitter generator assumes that
>> the instruction fields are declared in the instruction format in
>> the same order that operands are defined. This seems like a bad
>> dependence to me, and that TableGen should match
2007 Apr 18
0
[LLVMdev] CodeEmitterGen
On Apr 18, 2007, at 11:25 AM, Christopher Lamb wrote:
> I noticed that the TableGen code emitter generator assumes that the
> instruction fields are declared in the instruction format in the
> same order that operands are defined. This seems like a bad
> dependence to me, and that TableGen should match the name of field
> declared in the instruction with the name of the
2007 Apr 18
2
[LLVMdev] CodeEmitterGen
I noticed that the TableGen code emitter generator assumes that the
instruction fields are declared in the instruction format in the same
order that operands are defined. This seems like a bad dependence to
me, and that TableGen should match the name of field declared in the
instruction with the name of the operand in order to determine which
operand of the MI to use
.
See
2009 Mar 16
0
[LLVMdev] MachO and ELF Writers/MachineCodeEmittersarehard-codedinto LLVMTargetMachine
Aaron, I mailed in the same mail twice (by mistake), you answered both
copies. Differently!
In any case, I've re-read what exists. I'm dumping what I understand
here, so that we can discuss in detail. I'm using MachO as the example
object format, as the ELF code is totally broken and outdated. Lets
use the following as the basis for our discussion?
There are 3 classes which
2009 Mar 16
2
[LLVMdev] MachO and ELF Writers/MachineCodeEmittersarehard-codedinto LLVMTargetMachine
>> Sorry, I disagree actually the MachineCodeEmitter or the
>> 'MachineCodeWritter' does not do any file handling at all. Do look at the
>> code for the MachineCodeWritter and you will see it only writes to memory
>> and if it reaches the end of the allotted memory I believe higher ordered
>> logic reallocates a larget buffer and starts again from scratch.
2008 Jan 03
2
[LLVMdev] Building LLVM on Windows
Hello,
Thanks to recent changes in the SVN, I was able to successfully build
LLVM under Windows in the following environments:
1. Cygwin;
2. MinGW/MSYS;
3. "gcc -mno-cygwin" (a.k.a MinGW on Cygwin).
For 3., I've had to make a few manual changes to the build system. Care
is needed because non-Cygwin external commands require Windows paths and
Cygwin's make does not like path
2006 Oct 01
2
[LLVMdev] Instruction descriptions question
Hi,
I'm trying to implement a new backend for an embedded CISC processor.
Therefore I thought that it makes sense to take X86 target as a basis,
to save some time.
But when I look into the X86InstrInfo.td, I have a very strong feeling
that it is one of the most complex instruction set descriptions
compared to other targets. I can imagine that this is due to the
complexity of X86's
2006 Oct 02
0
[LLVMdev] Instruction descriptions question
On Sun, 1 Oct 2006, Roman Levenstein wrote:
> I'm trying to implement a new backend for an embedded CISC processor.
> Therefore I thought that it makes sense to take X86 target as a basis,
> to save some time.
Ok. Note that the X86 backend is one of the most complex though, because
it supports several subtargets and ABIs, which makes it more complex than
some other targets.
>
2013 Mar 20
1
[LLVMdev] changing passes and changing subtargets on a per function basis
I'm implementing this capability to allow switching between mips32 and
mips16 code generation on a per function basis (should be useful for arm
to thumb switching too).
The problem is that while various things are done on a per function
basis, there are two passes registered on a per module basis (target
lowering and instruction selection).
With the new attribute scheme, we can wake up
2013 Aug 19
0
[LLVMdev] where are all the Triple info of ARM subtargets?
hi,
i am trying to find out all the Triple (CPU information) of all the ARM
subtargets supported by LLVM 3.3.
to do this, i traced all the calls to class ARMSubtarget(), because this
class initialized the Triple. i supposed that all the ARM machines need to
initialize their own Triple info with ARMSubtarget(). however, to my
frustrated, this doesnt seem true, and i still cannot find them
2009 Mar 16
2
[LLVMdev] MachO and ELFWriters/MachineCodeEmittersarehard-codedinto LLVMTargetMachine
> Aaron, I mailed in the same mail twice (by mistake), you answered both
> copies. Differently!
>
> In any case, I've re-read what exists. I'm dumping what I understand
> here, so that we can discuss in detail. I'm using MachO as the example
> object format, as the ELF code is totally broken and outdated. Lets
> use the following as the basis for our discussion?
2019 Mar 13
2
Per-function subtargets
I've been trying to understand the current state of subtargets and
subtarget features in LLVM. It seems like the presence of "target-cpu"
and "target-features" attributes on IR functions are currently intended
to take precedence over the module-level (TargetMachine) versions. See
X86TargetMachine::getSubtargetImpl for an example of this. However, this
feels like it is
2015 Dec 15
2
How to efficiently share data (a dataframe) between R and Java
Dear all,
thank you for your hints. I would prefer to do not use Rserve as Dirk
mentioned.
@Simon
I have full control over the Java implementation - I can adapt the code
that I use for the communication R <-> Java.
> You can natively access structures on each side. The fastest way is to
> use R representation (column-oriented) in Java - that is much faster
> than any kind of
2015 Dec 06
3
How to efficiently share data (a dataframe) between R and Java
Dear all,
in our ongoing project we use Java implementations of several
algorithms. We also provide a ?wrapper? implemented as an R package
using rJava (https://github.com/jaroslav-kuchar/rCBA). Based on our
recent experiments, the significant portion of time is spent on copying
a dataframe from R to Java. The Java implementation needs access to the
source dataframe.
I have tested several
2011 Apr 03
2
Puppetmaster behind ssh with remote port forward
Hi Folks,
I''m trying to setup a test envoriment which is composed by a
puppetmaster running in my laptop (Macos Snow Leopard) and a puppet
client running on a EC2 instance at Amazon. In order to allow the
client to talk with the master I''m using an SSH Remote port forward,
ie I login into from the laptop into the EC2 instance witha "-R
8140:localhost:8140" flag.
This
2003 Sep 16
1
how to identify huge downloads ?
hello ...
how can I identify huge downloads on link to automticly move them to low priority queue ? somethink like combination rate and duration of session
Thanks
2008 Apr 12
1
Solving ODEs
Hello.
I'm solving ODEs in R. I need "as many methods as possible",
so I downloaded the Fortran functions from http://www.netlib.org/ode/.
Then I created DLLs and dyn.loaded them to R. Problem is that
I don't know how to use them. I've been trying for many days
and can't solve it. So I would be very glad if you could give me
some link (or whatever) where I can see how to
2012 Sep 26
1
[LLVMdev] Add --program-prefix support with AC_CANONICAL_TARGET override.
Adding --program-prefix support to the autoconf build has been an adventure.
A patch was applied. It worked on the usual llvm bots, but failed on
other bots with different configure options.
The patch was reverted as it broke on bots specifying --build, --host,
and --target in configure.
An option is proposed here to change the behavior of program-prefix to
it's normal behavior when