similar to: [LLVMdev] Interprocedural Register Allocation

On Oct 4, 2012, at 2:47 AM, Madhusudan C.S <madhusudancs at gmail.com> wrote: > However, I was reading the DeveloperPolicy page and the policy for making major > changes asks the developers to discuss the work here before proceeding. So, I am > writing this mail to kickoff a discussion. I would really like to contribute to LLVM and > I think this is a good place for me to start.

Hi Jakob, On Thu, Oct 4, 2012 at 1:31 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote: > > On Oct 4, 2012, at 2:47 AM, Madhusudan C.S <madhusudancs at gmail.com> wrote: > > However, I was reading the DeveloperPolicy page and the policy for making > major > changes asks the developers to discuss the work here before proceeding. > So, I am > writing this

On Oct 4, 2012, at 2:27 PM, "Madhusudan C.S" <madhusudancs at gmail.com> wrote: > Basically, the PrologEpilogInsertion pass will add a bit mask to MachineModuleInfo describing which registers are clobbered by the function being compiled. Later, when compiling the callers, that bit mask is used to initialize the regmask operands on call instructions. > > So the idea is to

Hi Jakob, On Thu, Oct 4, 2012 at 2:31 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote: > > On Oct 4, 2012, at 2:27 PM, "Madhusudan C.S" <madhusudancs at gmail.com> > wrote: > > Basically, the PrologEpilogInsertion pass will add a bit mask to >> MachineModuleInfo describing which registers are clobbered by the function >> being compiled. Later,

On Oct 31, 2012, at 1:41 PM, Madhusudan C.S <madhusudancs at gmail.com> wrote: > I have spent last 4 weeks trying to figure out how to implement > Interprocedural Register Allocation. I must admit that I was really > overwhelmed with LLVM's codebase while trying to figure this out :) > There is so much to know! I think I have reached a point where I > have some sort of

Hi Jakob, I have been trying to learn how the CodeGen passes work and I am playing around with the -debug-pass option. I tried implementing a bare CallGraphSCCPass based Pass in the CodeGen which basically does nothing for now. I mostly tried to replicate what RegAlloc passes do. I did this instead of modifying the existing RegAlloc passes to use CallGraphSCCPass because that was becoming way too

Hi Jakob, I have spent last 4 weeks trying to figure out how to implement Interprocedural Register Allocation. I must admit that I was really overwhelmed with LLVM's codebase while trying to figure this out :) There is so much to know! I think I have reached a point where I have some sort of basic understanding of what needs to be done, but I need some help from here on. So here is the

*Vivek Pandya* On Wed, May 11, 2016 at 4:01 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > ------------------------------ > > *From: *"vivek pandya" <vivekvpandya at gmail.com> > *To: *"Mehdi Amini" <mehdi.amini at apple.com> > *Cc: *"Hal Finkel" <hfinkel at anl.gov>, "Quentin Colombet" < > qcolombet at

*Vivek Pandya* On Wed, May 18, 2016 at 11:25 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On May 18, 2016, at 10:46 AM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > > *Vivek Pandya* > > > On Wed, May 11, 2016 at 4:01 PM, Hal Finkel <hfinkel at anl.gov> wrote: > >> >> ------------------------------ >> >>

> On May 18, 2016, at 11:00 AM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > > Vivek Pandya > > > On Wed, May 18, 2016 at 11:25 PM, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: > >> On May 18, 2016, at 10:46 AM, vivek pandya <vivekvpandya at gmail.com <mailto:vivekvpandya at

> On May 11, 2016, at 3:31 AM, Hal Finkel via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > From: "vivek pandya" <vivekvpandya at gmail.com> > To: "Mehdi Amini" <mehdi.amini at apple.com> > Cc: "Hal Finkel" <hfinkel at anl.gov>, "Quentin Colombet" <qcolombet at apple.com>, "llvm-dev"

*Vivek Pandya* On Wed, May 11, 2016 at 10:02 AM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > *Vivek Pandya* > > > On Wed, May 11, 2016 at 9:43 AM, Mehdi Amini <mehdi.amini at apple.com> > wrote: > >> >> On May 10, 2016, at 6:06 PM, Hal Finkel <hfinkel at anl.gov> wrote: >> >> >> >>

Hello, I have written following code to check each register if it is used by machineFunction or not : MachineRegisterInfo *MRI = &MF.getRegInfo(); TargetRegisterInfo *TRI = (TargetRegisterInfo *)MF.getSubtarget().getRegisterInfo(); const TargetMachine &TM = MF.getTarget(); const MCRegisterInfo *MCRI = TM.getMCRegisterInfo(); DEBUG(dbgs() << "Function Name : " <<

----- Original Message ----- > From: "vivek pandya" <vivekvpandya at gmail.com> > To: "Quentin Colombet" <qcolombet at apple.com> > Cc: "Hal Finkel" <hfinkel at anl.gov>, "llvm-dev" > <llvm-dev at lists.llvm.org>, "Matthias Braun" <matze at braunis.de>, > "Mehdi Amini" <mehdi.amini at

----- Original Message ----- > From: "vivek pandya" <vivekvpandya at gmail.com> > To: "Matthias Braun" <matze at braunis.de> > Cc: "Hal Finkel" <hfinkel at anl.gov>, "llvm-dev" > <llvm-dev at lists.llvm.org> > Sent: Wednesday, May 11, 2016 1:14:07 PM > Subject: Re: [llvm-dev] [GSoC 2016] Interprocedural Register

Yes there is also MachineRegisterInfo::UsedPhysRegMask which should be the union of all regmasks in the function. > On May 11, 2016, at 10:47 AM, Hal Finkel via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > > From: "Matthias Braun" <matze at braunis.de> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: "vivek pandya"

----- Original Message ----- > From: "vivek pandya" <vivekvpandya at gmail.com> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: "llvm-dev" <llvm-dev at lists.llvm.org>, "Matthias Braun" > <matze at braunis.de>, "Mehdi Amini" <mehdi.amini at apple.com>, "Quentin > Colombet" <qcolombet at

On Wed, May 25, 2016 at 3:53 AM, Hal Finkel <hfinkel at anl.gov> wrote: > > ------------------------------ > > *From: *"vivek pandya" <vivekvpandya at gmail.com> > *To: *"Quentin Colombet" <qcolombet at apple.com> > *Cc: *"Hal Finkel" <hfinkel at anl.gov>, "llvm-dev" <llvm-dev at lists.llvm.org>, >

On Wed, May 25, 2016 at 8:44 AM, Hal Finkel <hfinkel at anl.gov> wrote: > > ------------------------------ > > *From: *"vivek pandya" <vivekvpandya at gmail.com> > *To: *"Hal Finkel" <hfinkel at anl.gov> > *Cc: *"llvm-dev" <llvm-dev at lists.llvm.org>, "Matthias Braun" < > matze at braunis.de>, "Mehdi

Dear Mentors, Please help me to understand our plan to implement Interprocedural Register allocator by propogating register usage info. While writing this mail I am considering all previous discussion over llvm-dev and IRC. 1) A MachineFunction pass to be executed POST-RA to collect the information about the used Registers. 2) An Immutable pass which will store reg usage info collected by