similar to: [LLVMdev] [PATCH][Review request] tablegen: extend list fields

If you are changing the syntax, please update the BNF in the comments. --Sean Silva On Wed, Sep 12, 2012 at 6:16 PM, Akira Hatanaka <ahatanak at gmail.com> wrote: > The attached patch adds a construct that enables extending the base class' > lists rather than completely overwriting them. > The patch hasn't gone through extensive testing yet (other than running make >

Please take a look at the attached patch. I updated the BNF and added comments in the code. On Wed, Sep 12, 2012 at 4:58 PM, Sean Silva <silvas at purdue.edu> wrote: > If you are changing the syntax, please update the BNF in the comments. > > --Sean Silva > > On Wed, Sep 12, 2012 at 6:16 PM, Akira Hatanaka <ahatanak at gmail.com> > wrote: > > The attached

Dear LLVMers, we have released a tool that uses LLVM to insert OpenACC or OpenMP 4.0 directives in programs. You can use the tool online here: http://cuda.dcc.ufmg.br/dawn/. Our tool, dawn-cc, analyzes the LLVM IR to infer the sizes of memory chunks, and to find dependences within loops. After that, we use debug information to translate the low-level information back into annotations that we

Hi, > On Dec 31, 2016, at 8:33 AM, Fernando Magno Quintao Pereira via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Dear LLVMers, > > we have released a tool that uses LLVM to insert OpenACC or OpenMP > 4.0 directives in programs. You can use the tool online here: > http://cuda.dcc.ufmg.br/dawn/. Our tool, dawn-cc, analyzes the LLVM IR > to infer the sizes of

Dear Mehdi, I've changed your example a little bit: float saxpy(float a, float *x, float *y, int n) { int j = 0; for (int i = 0; i < n; ++i) { y[j] = a*x[i] + y[I]; // Change 'I' into 'j'? ++j; } } I get this code below, once I replace 'I' with 'j'. We are copying n positions of both arrays, 'x' and 'y': float saxpy(float a,

> On Jan 3, 2017, at 7:17 AM, Jonathan Roelofs <jonathan at codesourcery.com> wrote: > > > > On 12/31/16 12:37 PM, Fernando Magno Quintao Pereira via llvm-dev wrote: >> Dear Mehdi, >> >> I've changed your example a little bit: >> >> float saxpy(float a, float *x, float *y, int n) { >> int j = 0; >> for (int i = 0; i < n;

Hello R community, I am using R for creating a model using optimization. I would like to ask if there is R-function/package for solving the problem below: Minimize sum(abs(exp^(Ai1 x1 + Ai2 x2 + ... + Aim xm - bi) - 1)), for each i = 1, ..., n. subject to Ai1 x1 + Ai2 x2 + ... + Ajm xm - bi <= c, where c is a scalar. (x is a vector of variables, A is nxm matrix, b is a vector)

Hello LLVM, I'm playing with a new ISD::OPAQUE instruction to make hoisting first class and eliminate a lot of tweaky flag setting/checking around opaque constants. It's going well for the IR and x86, but I now I need to sort out details for all the other targets. To start, can someone please advise on the AAarch64 equivalent of these X86 patterns? // Opaque values become mov immediate

Hi I have a problem in R that I have been trying to solve but without success. I am trying to join two tables on two variables : an ID and a date (optional) that will be common between the two tables In SQL (and SAS PROC SQL) I am a frequent user of the "select" command and I am used to the following nomenclature : select a.*, b.c, b.y, b.z from table1 a, table2 b where

Hi Jonas, > It is interesting to find this in the ARM backend, considering your answer. The ARM backend doesn't use the DFA packetizer. It's only used by Hexagon. At this point, there is no plan to address thisin the DFA packetizer since none of the supported targets needthe functionality. Thanks -Anshu --- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,

Hi, I looked a bit through the mail archives, and found this question answered in Oct 2011 (see below). It is interesting to find this in the ARM backend, considering your answer. Can you give more information about for example is this a temporary deficiency in the DFAPacketizer? What is the IIC_iMOVi itinerary doing below? Thanks, Jonas Thu Oct 6 15:11:25 CDT 2011: Hello Hal. > Is there

Jonas, At this point, the DFA packetizer models a simple VLIW architecture and does not accommodate multiple stages. That's the reason for the behavior you're seeing. -Anshu --- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation *From:*llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] *On Behalf Of *Jonas

Hi Anshu, Would there be any interest in extending this algorithm to handling more extensive models, such as VLIW scheduling based on FU's and bundle space... ie handle multiple stages ? I might do it and commit, if there is acceptance and guidance... Jonas ________________________________ From: Anshuman Dasgupta [mailto:adasgupt at codeaurora.org] Sent: Tuesday, February 12, 2013 4:47 PM

Hi, I'm trying to write an LLVM backend using LLVM's retargetable code generator, and I'm confused about how the SelectionDAG works. Let me give you an example from the SPARC backend (as this is what is often mentioned in the documentation). This is how the "branch always" instruction is defined: def BA : BranchSP<0b1000, (ins brtarget:$dst),