Displaying 20 results from an estimated 7000 matches similar to: "[LLVMdev] Bitcasts between pointers with different address spaces"
2012 Sep 07
0
[LLVMdev] Bitcasts between pointers with different address spaces
Hi,
I don't think we should make bit casts between pointers with different address spaces illegal. Address spaces are not required to be disjoint. In the N1169 spec, it says
A non-null pointer into an address space A can be cast to a pointer into another address space B, but such a cast is undefined if the source pointer does not point to a location in B.
If the address spaces
2012 Sep 08
2
[LLVMdev] Bitcasts between pointers with different address spaces
Mon Ping Wang wrote:
> Hi,
>
> I don't think we should make bit casts between pointers with different
> address spaces illegal. Address spaces are not required to be disjoint.
> In the N1169 spec, it says
> A non-null pointer into an address space A can be cast to a pointer into
> another address space B, but such a cast is undefined if the source
> pointer does not
2012 Sep 08
2
[LLVMdev] Bitcasts between pointers with different address spaces
Mon Ping Wang wrote:
>
> On Sep 7, 2012, at 11:10 PM, Nick Lewycky<nicholas at mxc.ca> wrote:
>
>> Mon Ping Wang wrote:
>>> Hi,
>>>
>>> I don't think we should make bit casts between pointers with different
>>> address spaces illegal. Address spaces are not required to be disjoint.
>>> In the N1169 spec, it says
>>> A
2012 Sep 08
0
[LLVMdev] Bitcasts between pointers with different address spaces
On Sep 7, 2012, at 11:10 PM, Nick Lewycky <nicholas at mxc.ca> wrote:
> Mon Ping Wang wrote:
>> Hi,
>>
>> I don't think we should make bit casts between pointers with different
>> address spaces illegal. Address spaces are not required to be disjoint.
>> In the N1169 spec, it says
>> A non-null pointer into an address space A can be cast to a
2012 Sep 08
0
[LLVMdev] Bitcasts between pointers with different address spaces
On Sep 8, 2012, at 12:21 AM, Nick Lewycky <nicholas at mxc.ca> wrote:
> Mon Ping Wang wrote:
>>
>> On Sep 7, 2012, at 11:10 PM, Nick Lewycky<nicholas at mxc.ca> wrote:
>>
>>> Mon Ping Wang wrote:
>>>> Hi,
>>>>
>>>> I don't think we should make bit casts between pointers with different
>>>> address
2012 Sep 20
3
[LLVMdev] Proposal: New IR instruction for casting between address spaces
If I don't bring in TargetData, then there is no way for me to verify the address space size in the verifier or in the auto-upgrade mechanisms.
> -----Original Message-----
> From: Eli Friedman [mailto:eli.friedman at gmail.com]
> Sent: Thursday, September 20, 2012 2:32 PM
> To: Villmow, Micah
> Cc: Chris Lattner; Mon Ping Wang; llvm-commits at cs.uiuc.edu;
> llvmdev at
2012 Sep 14
0
[LLVMdev] Proposal: New IR instruction for casting between address spaces
> -----Original Message-----
> From: Chris Lattner [mailto:clattner at apple.com]
> Sent: Thursday, September 13, 2012 11:53 PM
> To: Mon Ping Wang
> Cc: Villmow, Micah; llvmdev at cs.uiuc.edu Mailing List
> Subject: Re: [LLVMdev] Proposal: New IR instruction for casting between
> address spaces
>
>
> On Sep 13, 2012, at 5:55 PM, Mon Ping Wang <monping at
2012 Sep 20
2
[LLVMdev] Proposal: New IR instruction for casting between address spaces
Ping!
> -----Original Message-----
> From: Villmow, Micah
> Sent: Tuesday, September 18, 2012 4:12 PM
> To: 'Chris Lattner'; 'Mon Ping Wang'
> Cc: 'llvm-commits at cs.uiuc.edu'; 'llvmdev at cs.uiuc.edu'
> Subject: RE: [LLVMdev] Proposal: New IR instruction for casting between
> address spaces
>
> Resending since I got an error.
>
2012 Sep 14
6
[LLVMdev] Proposal: New IR instruction for casting between address spaces
On Sep 13, 2012, at 5:55 PM, Mon Ping Wang <monping at apple.com> wrote:
>>> The pointer size is target dependent so it seems strange to choose an arbitrary size to convert to and from. Are you making a practical argument that 64b is sufficient on all machines so all targets can use that? In other words, pointers > 64 doesn't make any sense in terms of the address space? (A
2012 Sep 20
0
[LLVMdev] Proposal: New IR instruction for casting between address spaces
On Thu, Sep 20, 2012 at 3:30 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> If I don't bring in TargetData, then there is no way for me to verify the address space size in the verifier or in the auto-upgrade mechanisms.
And that's why I didn't like this approach in the first place.
-Eli
>> -----Original Message-----
>> From: Eli Friedman
2012 Sep 20
0
[LLVMdev] Proposal: New IR instruction for casting between address spaces
We can't add a circular dependency between Target and VMCore.
-Eli
On Thu, Sep 20, 2012 at 8:21 AM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> Ping!
>
>> -----Original Message-----
>> From: Villmow, Micah
>> Sent: Tuesday, September 18, 2012 4:12 PM
>> To: 'Chris Lattner'; 'Mon Ping Wang'
>> Cc: 'llvm-commits at
2012 Sep 20
1
[LLVMdev] Proposal: New IR instruction for casting between address spaces
On Thu, 20 Sep 2012 15:34:52 -0700
Eli Friedman <eli.friedman at gmail.com> wrote:
> On Thu, Sep 20, 2012 at 3:30 PM, Villmow, Micah
> <Micah.Villmow at amd.com> wrote:
> > If I don't bring in TargetData, then there is no way for me to
> > verify the address space size in the verifier or in the
> > auto-upgrade mechanisms.
>
> And that's why I
2012 Aug 30
2
[LLVMdev] FW: RFC: Supporting different sized address space arithmetic
> -----Original Message-----
> From: Eli Friedman [mailto:eli.friedman at gmail.com]
> Sent: Thursday, August 30, 2012 3:43 PM
> To: Villmow, Micah
> Cc: LLVM Developers Mail
> Subject: Re: [LLVMdev] FW: RFC: Supporting different sized address space
> arithmetic
>
> On Thu, Aug 30, 2012 at 3:27 PM, Villmow, Micah <Micah.Villmow at amd.com>
> wrote:
> >
2013 Aug 08
5
[LLVMdev] Address space extension
On 08/08/2013 02:52 PM, Micah Villmow wrote:
> This is something I proposed last year, so you might want to read up on that discussion first.
>
> You can find it here:
> http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-September/053277.html
Uhm... I read the discussion, probably I've not understood the problem
well: the conclusion (it has been committed?) is that to handle address
2012 Aug 30
0
[LLVMdev] FW: RFC: Supporting different sized address space arithmetic
On Thu, Aug 30, 2012 at 3:51 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
>
>
>> -----Original Message-----
>> From: Eli Friedman [mailto:eli.friedman at gmail.com]
>> Sent: Thursday, August 30, 2012 3:43 PM
>> To: Villmow, Micah
>> Cc: LLVM Developers Mail
>> Subject: Re: [LLVMdev] FW: RFC: Supporting different sized address space
>>
2012 Aug 30
1
[LLVMdev] FW: RFC: Supporting different sized address space arithmetic
On Thu, 30 Aug 2012 15:58:54 -0700
Eli Friedman <eli.friedman at gmail.com> wrote:
> On Thu, Aug 30, 2012 at 3:51 PM, Villmow, Micah
> <Micah.Villmow at amd.com> wrote:
> >
> >
> >> -----Original Message-----
> >> From: Eli Friedman [mailto:eli.friedman at gmail.com]
> >> Sent: Thursday, August 30, 2012 3:43 PM
> >> To: Villmow,
2012 Jul 30
0
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
"Villmow, Micah" <Micah.Villmow at amd.com> writes:
> Sorry, <4 x i8> should convert to a <1 x i32>.
Why? I'm really confused.
Shouldn't this converts to a <4 x i32>?
-Dave
2012 Jul 30
4
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
Sorry, <4 x i8> should convert to a <1 x i32>. What currently is happening is that it is returning a <2 x i32> because <1 x i32> does not exist.
Micah
> -----Original Message-----
> From: Rotem, Nadav [mailto:nadav.rotem at intel.com]
> Sent: Monday, July 30, 2012 10:51 AM
> To: Villmow, Micah; Developers Mailing List
> Subject: RE: Vector promotion broken
2012 Sep 12
2
[LLVMdev] Proposal: New IR instruction for casting between address spaces
> -----Original Message-----
> From: Mon P Wang [mailto:monping at apple.com]
> Sent: Wednesday, September 12, 2012 1:12 PM
> To: Villmow, Micah
> Cc: Dan Gohman; llvmdev at cs.uiuc.edu
> Subject: Re: [LLVMdev] Proposal: New IR instruction for casting between
> address spaces
>
> Hi,
>
> On Sep 11, 2012, at 2:30 PM, Villmow, Micah wrote:
>
> >
> >
2012 Jul 30
1
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
The comments in the code state it should do bitcast, op, then bitcast, not extend, op and truncate.
"SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
// Vector "promotion" is basically just bitcasting and doing the operation
// in a different type. For example, x86 promotes ISD::AND on v2i32 to
// v1i64."
So following the same logic <4 x i8> bitcasts into a