similar to: [LLVMdev] Question regarding ReplaceValueWith and ReplaceNodeResults

Displaying 20 results from an estimated 800 matches similar to: "[LLVMdev] Question regarding ReplaceValueWith and ReplaceNodeResults"

2012 Sep 02
0
[LLVMdev] Question regarding ReplaceValueWith and ReplaceNodeResults
Hi Pranav, >> as well as what Eli said, ReplaceNodeResults requires (IIRC) the new node > to >> have the same type as the old node, which doesn't seem to be the case >> here. > > Are you sure ? I see ReplaceNodeResults being called from functions such as > CustomWidenLowerNode and CustomLowerNode. > In the former, we are clearly expecting a change in type,
2012 Aug 31
3
[LLVMdev] Question regarding ReplaceValueWith and ReplaceNodeResults
Hi, I am defining Hexagons version of ReplaceNodeResults to change the a node of the type A: i8 = INTRINSIC_WO_CHAIN ... , ... , To B: SIGN_EXTEND (A) After returning from my function, the type legalizer calss ReplaceValuesUsesWith to replace the uses of A with B. Unfortunately, it replaces the use of A in the new node B too. So the node now is B: SIGN_EXTEND(B) , which is clearly bad and the
2012 Aug 31
0
[LLVMdev] Question regarding ReplaceValueWith and ReplaceNodeResults
On Fri, Aug 31, 2012 at 2:48 PM, Pranav Bhandarkar <pranavb at codeaurora.org> wrote: > Hi, > > I am defining Hexagons version of ReplaceNodeResults to change the a node of > the type > A: i8 = INTRINSIC_WO_CHAIN ... , ... , > > To > B: SIGN_EXTEND (A) > > After returning from my function, the type legalizer The type legalizer asked your target to replace an
2020 Jan 28
2
Handling node through TargetLowering::LowerOperation vs TargetLowering::ReplaceNodeResults
Thank you Craig for explanation. Could be the same algorithm used for custom legalizing given node in LowerOperation and ReplaceNodeResults in case results and inputs of the node are illegal? Or actually such situation is impossible and for given node either LowerOperation or ReplaceNodeResults can be only called? Przemek wt., 28 sty 2020, 18:48 użytkownik Craig Topper <craig.topper at
2020 Jan 28
2
Handling node through TargetLowering::LowerOperation vs TargetLowering::ReplaceNodeResults
Hi, I see that for different targets in classes which inherits from TargetLowering there are implemented both methods: LowerOperation and ReplaceNodeResults What decides that for one given ISD we have to add handling in LowerOperation and for other in ReplaceNodeResults, when for both SetOperationAction is configured to be Custom? Is it related with number of results of given operation and
2016 Jan 25
1
Return value from TargetLowering::LowerOperation?
Hi, On 01/22/2016 05:02 PM, Tom Stellard wrote: > On Fri, Jan 22, 2016 at 01:58:49PM +0100, Mikael Holmén via llvm-dev wrote: >> Hi, >> >> I'm a litle bit puzzled by the TargetLowering::LowerOperation function, >> and what different callers of this function assumes about the returned >> value. >> > SelectionDAGLegalize::LegalizeOp() is your best
2016 Jan 22
3
Return value from TargetLowering::LowerOperation?
Hi, I'm a litle bit puzzled by the TargetLowering::LowerOperation function, and what different callers of this function assumes about the returned value. In several places it seems like it is assumed that LowerOperation can return three kinds of values: * Something completely new. * SDValue() * The same SDValue as LowerOperation was called on. However in some places, e.g. in
2011 Jun 13
1
[LLVMdev] Modifying DAG in TargetLowering::ReplaceNodeResults()
Hi! I am trying to implement va_arg() on ppc32. Everything went smooth, except implementing va_arg() of 64bit int. Since i64 is not a legal type on ppc32 DAGTypeLegalizer::ExpandRes_VAARG() splits the va_arg(i64) into two i32 va_args. The problem with ppc32 va_arg is that it needs special "alignment" of its gpr pointer when the argument is i64. Ie. I need to know if I am lowering
2017 Sep 22
0
[Hexagon] Type Legalization
Hi Sanjay, thanks for this information. I did get a little bit further with the patch. However, Hexagon gives me headaches. I tried to limit the scope of the patch to the BeforeLegalizeTypes phase and Hexagon still reaches the unreachable. Hexagon tries to split or widen a vector type for a node with custom lowering where the unreachable arises from inside TargetLowering::ReplaceNodeResults
2017 Sep 22
2
[Hexagon] Type Legalization
Is VT a legal type on Hexagon? It looks like Hexagon may be setting SHL as Custom for every defined vector type. Try adding TLI.isTypeLegal(VT) too. ~Craig On Thu, Sep 21, 2017 at 10:06 PM, Haidl, Michael < michael.haidl at uni-muenster.de> wrote: > Hi Sanjay, > > thanks for this information. I did get a little bit further with the > patch. However, Hexagon gives me headaches.
2017 Sep 20
3
Updating LLVM Tests for Patch
There are multiple problems/questions here: 1. Make sure you've updated trunk to the latest rev before running update_llc_test_checks.py on lea-3.ll. Ie, I would only expect the output you're seeing if you're running the script on a version of that test file before r313631. After that commit, each RUN has its own check prefix, so there should be no conflict opportunity. 2. I
2017 Sep 22
0
[Hexagon] Type Legalization
Hi Craig, protecting the transformation with: if (TLI.isTypeLegal(VT) && TLI.isOperationLegal(ISD::SUB, VT) && TLI.isOperationLegal(ISD::ADD, VT) && TLI.isOperationLegal(ISD::SHL, VT) && TLI.isOperationLegal(ISD::SRA, VT)) { shows the same result. Michael On 22.09.2017 07:19, Craig Topper wrote: > Is VT a legal type on Hexagon?
2008 Aug 19
1
[LLVMdev] Type Legalizer - Load handling problem
On Tue, Aug 19, 2008 at 8:40 AM, Eli Friedman <eli.friedman at gmail.com> wrote: > On Tue, Aug 19, 2008 at 8:07 AM, sanjiv gupta > <sanjiv.gupta at microchip.com> wrote: >> On Mon, 2008-08-18 at 08:50 -0700, Eli Friedman wrote: >>> On Mon, Aug 18, 2008 at 6:31 AM, <Sachin.Punyani at microchip.com> wrote: >>> > assert(Res.getValueType() ==
2017 Sep 20
0
Updating LLVM Tests for Patch
Hi, I am currently working on a more or less intrusive patch (D37896), which pulls optimizations on multiplications from some back-ends, e.g., (mul x, 2^N + 1) => (add (shl x, N), x) in AArch64, into the DAGCombiner to have this optimization generic on all targets. However, running the LLVM Tests leads to 67 unexpected results. Am 19.09.2017 um 15:58 schrieb Sanjay Patel: > For the
2009 Jan 16
0
[LLVMdev] PIC16 backend for llvm 2.5
Hi Sanjiv, > Well the magnitude of the task is not small. > ExpandIntegerOperand() calls LowerOperation() to allow targets to handle > illegal operands. So we will need to change the interface of > LowerOperation() to pass an extra argument called Results, which is an > array of SDValue. Targets will push the result values in this array and > then we can replace values in
2009 Jan 16
2
[LLVMdev] PIC16 backend for llvm 2.5
> -----Original Message----- > From: Duncan Sands [mailto:baldrick at free.fr] > Sent: Friday, January 09, 2009 5:23 PM > To: Sanjiv Kumar Gupta - I00171 > Cc: llvmdev at cs.uiuc.edu > Subject: Re: PIC16 backend for llvm 2.5 > > Hi Sanjiv, > > > Well, the first email is here. > > > > http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon- >
2009 Jan 18
2
[LLVMdev] PIC16 backend for llvm 2.5
On Fri, 2009-01-16 at 10:03 +0100, Duncan Sands wrote: > Hi Sanjiv, > > > Well the magnitude of the task is not small. > > ExpandIntegerOperand() calls LowerOperation() to allow targets to handle > > illegal operands. So we will need to change the interface of > > LowerOperation() to pass an extra argument called Results, which is an > > array of SDValue.
2012 Jun 01
0
[LLVMdev] Predicate registers/condition codes question
Hi Sebastian, Le 25/05/2012 18:54, Sebastian Pop a écrit : > On Thu, May 24, 2012 at 5:40 PM, Sebastian Pop<spop at codeaurora.org> wrote: >> On Thu, May 24, 2012 at 5:06 PM, Hal Finkel<hfinkel at anl.gov> wrote: >>> Sebastian, >>> >>> First, it might be useful to look at what is done in the PowerPC >>> backend. PPC also has condition
2012 Sep 18
0
[LLVMdev] liveness assertion problem in llc
On Sep 18, 2012, at 1:45 PM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote: > I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
On Jun 13, 2012, at 1:15 PM, Sergei Larin <slarin at codeaurora.org> wrote: > Andy, > > You are probably right here – look at this – before phi elimination this code looks much more sane: > > # *** IR Dump After Live Variable Analysis ***: > # Machine code for function push: SSA > Function Live Outs: %R0 > > BB#0: derived from LLVM BB %entry >