similar to: [LLVMdev] Is cross-compiling for ARM on x86 with llvm/Clang possible?

On Sat, Jun 16, 2012 at 08:20:23PM +0900, Journeyer J. Joh wrote: > If the cross compiling is supported, is there any documentation on how to > do it? The short version is: assuming you have a cross-binutils installation using e.g. x86_64--netbsd-as and x86_64--netbsd-ld, you add a symlink called x86_64--netbsd-clang to clang and just call that with an appropiate --sysroot to make it find

Hello Gergö, Joerg and people on our list With your kind answer, I tried to build a hello world program for ARM(arm-none-linux-gnueabi) on my x86-64 PC. Thank you we verified the generated bitcode. The only thing remained is linking. Let me brief what I did so far. 1. Built Clang/llvm in a way explained in http://clang.llvm.org/get_started.html on Ubuntu 11.10 x86-64 PC 2. Downloaded gcc-4.0

Hello > ./clang -v -emit-llvm -ccc-host-triple arm-none-linux-gnueabi > -I/home/hum/Documents/Projects/llvm_clang/gnuarm-4.0.2/arm-elf/include > -L/home/hum/Documents/Projects/llvm_clang/gnuarm-4.0.2/arm-elf/bin hello.c You forgot about sysroot here. > /home/hum/Documents/Projects/llvm_clang/gnuarm-4.0.2/arm-elf/bin/ld: > unrecognised emulation mode: armelf_linux_eabi >

Hello, Thank you for your kind attention to my issue and your help. I changed the tool chain and tried again. And there is a little progress but still have some problem. Using --sysroot doesn't make clang use linker(ld) in the cross tool. Most important question is how I can make clang use cross tool linker. Let me show you my experiment and questions below. There are two questions. [Run]

On Sat, Jun 16, 2012 at 20:20:23 +0900, Journeyer J. Joh wrote: > I wonder if llvm/Clang can compile C or C++ for ARM from on x86. Yes. I use clang -emit-llvm -ccc-host-triple arm-unknown-linux-gnu -I /..arm../include/ to generate LLVM bitcode files for ARM. llc then automagically knows to generate ARM assembly, and ARM binutils take it from there. > If the cross compiling is supported,

A more pressing need is a pre-regalloc scheduler that can switch modes to balance reducing latency vs. reducing register pressure. The problem is the current approach is the scheduler is locked into one mode or the other. For x86, it generally makes sense to schedule for low register pressure. That is, until you are dealing with a block that are explicitly SSE code in 64-bit mode. In that case,

So I have a good understanding of what and how I want to do in the abstract sense. I am starting to gain a feel for the code base, and I see that I may have a allocator up and running much faster than I once thought thanks to the easy interfaces. What I need to know is how to access the machine register classes. Also, I need to know which virtual register is to be mapped into each specific

On Feb 5, 2010, at 2:01 AM, Gergö Barany wrote: > On Thu, Feb 04, 2010 at 13:59:08 -0800, Evan Cheng wrote: >> A more pressing need is a pre-regalloc scheduler that can switch modes to >> balance reducing latency vs. reducing register pressure. > > Right. I'm actually working on implementing a variant of IPS (Goodman and > Hsu, Code scheduling and register allocation

On Thu, Feb 04, 2010 at 13:59:08 -0800, Evan Cheng wrote: > A more pressing need is a pre-regalloc scheduler that can switch modes to > balance reducing latency vs. reducing register pressure. Right. I'm actually working on implementing a variant of IPS (Goodman and Hsu, Code scheduling and register allocation in large basic blocks, http://doi.acm.org/10.1145/55364.55407) based on the

On Sat, Aug 28, 2010 at 16:20:42 -0400, Jeff Kunkel wrote: > What I need to know is how to access the machine register classes. Also, I > need to know which virtual register is to be mapped into each specific > register class. I assume there is type information on the registers. I need > to know how to access it. MachineRegisterInfo::getRegClass will give you the TargetRegisterClass

Thanks for the information. I still don't know how do I partition registers into different classes from the virtual registers? For instance, I have the function who which iterates over the instructions, but I don't know how to write the function which returns the different register class. void RAOptimal::Gather(MachineFunction &Fn) { // Gather just iterates over the blocks,

Hi Joerg, Thank you very much! I finally found a working command string to cross-compile for ARM on x86. ./clang -v --save-temps -ccc-host-triple arm-none-linux-gnueabi --sysroot=/home/hum/Documents/Projects/arm_toolchain/arm-2010.09/arm-none-linux-gnueabi/libc -gcc-toolchain /home/hum/Documents/Projects/arm_toolchain/arm-2010.09 hello.c -o hello Above works fine! Important options are

Hi, Paul Curtis wrote: > If you read the Arm Architecture document for ARMv5, it states for MUL: > > "Operand restriction: Specifying the same register for <Rd> and <Rm> was > previously described as producing UNPREDICTABLE results. There is no > restriction in ARMv6, and it is believed all relevant ARMv4 and ARMv5 > implementations do not require this

Hello, is it possible to compile just an subproject? For example, just llc or lli? Cheers. Beckert. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120503/c20aa7b1/attachment.html>

Hello Everyone, Would you please send me any links to documentation on LLVM stack? I am particularly interested in knowing how each instruction in an LLVM bit code file(.ll file) affects its stack. To be specific, is it possible to map an LLVM program as operations on a stack? Thanks, Amruth

Thanks andrew for the answer. I would like to generate code for Cortex-A9 that don't use neon for fp computation but vfpv3 -d16. I've tried some combination of -mattr=+neon,-neonfp,+vfp3,+d16 but couldn't get ".fpu vfpv3-d16" directive generated in assembly file. Do you know how to make it happen ? Best Regards Seb From: Andrew Trick [mailto:atrick at apple.com] Sent:

All, I apologize if this is an inappropriate question for this mailing list. If so, please recommend an appropriate place to post the question. I'm also somewhat new to LLVM, so I could have some pretty fundamental misunderstandings about what I am trying to do. I have searched for information on the llvm.org website (user's guide, programmer's manual and doxygen documentation),

Hello, With your kind concern and help, I now can make a binary for ARM target. ./clang -v --save-temps -ccc-host-triple arm-none-linux-gnueabi --sysroot=/home/hum/Documents/Projects/arm_toolchain/arm-2010.09/arm-none-linux-gnueabi/libc -gcc-toolchain /home/hum/Documents/Projects/arm_toolchain/arm-2010.09 hello.c -o hello The build command is shown above. After that, I prepared an ARM laptop,

Hi, thank you for your explanations. In order to get a pre-RA scheduling, I would need something like: - LiveVars - PhiElim - TwoAddr - LiveIntervals - Coalescing - Scheduler (new) - SlotIndexing - LiveIntervals2 (new) - RegAllocMy qeustion then is, is it really so difficult to create the live intervals information, with modifications to the original algorithm, or even from scratch?

Hello list I have questions about compiling Clang+llvm. I compile as the link below instructs. http://clang.llvm.org/get_started.html I do on Ubuntu 12.04. `time make -j5` prints for about 13 minutes to compile a brand new version of Clang+llvm. And after this I edit some C++ code(clang/tools/driver/driver.cpp) and compiles using the very same makefile which was used above sentence. But this