similar to: [LLVMdev] MBlaze select_cc lowering question.

________________________________ From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Chris Lattner Sent: Friday, September 19, 2008 10:49 AM To: LLVM Developers Mailing List Subject: Re: [LLVMdev] Custom Opcodes versus built-in opcodes On Sep 18, 2008, at 4:04 PM, Villmow, Micah wrote: I am using lowering instructions and using custom opcodes that

Can you please post the code to split a MachineBasicBlock? I am trying to split a MachineBasicBlock at a specific instruction in the MBB, let us say, into MBB1 and MBB2. This instruction should go into MBB2. Also MBB1 should have an unconditional branch to MBB2 as the terminator. (quite similar to splitBasicBlock in BasicBlock.cpp) Meanwhile, I am trying to come up with a variant of

> Your patch looks very clean. Some comments: Heh, Jakob was faster :) > - I think you have some literal tabs in your instruction descriptions. The tabs can be seen in some other places as well. Also, there is a "mix" of coding conventions in the files. It will be really nice to use only one :) > - Your tests are nice, but you could use some more of them. I would recommend

On Sep 19, 2008, at 11:35 AM, Villmow, Micah wrote: > Make sure to use DAG.getTargetNode() with custom opcodes. "target" > nodes are encoded with an implicit delta added to their enum value. > > Is this documented anywhere that getTargetNode is the preferred > method to use in a Custom Lowering function? Even the other backends > use getNode in their lowering

> what does "refuses to compile" mean? I.e. what error do you get? > Specifically I get this message when compiling with the default -mattr: Call result #2 has unhandled type i32 UNREACHABLE executed at CallingConvLower.cpp:162! 0 llc 0x0000000100a1e115 PrintStackTrace(void*) + 38 1 llc 0x0000000100a1e6d0 SignalHandler(int) + 254 2

On Jan 30, 2010, at 6:49 AM, Anton Korobeynikov wrote: >> Your patch looks very clean. Some comments: > Heh, Jakob was faster :) I have taken care of everything Jakob mentioned except the extra test cases. I will get to these as soon as I can. > >> - I think you have some literal tabs in your instruction descriptions. > The tabs can be seen in some other places as well.

Hi Josef, > Okay, I've done a lot more testing and I now have a .bc file that compiles for x86, sparc, mips but refuses to compile for the mblaze and powerPC backends because of the calling convention. Is there anyone that would know how to fix the microblaze calling convention or point me in the right direction on how to fix it? what does "refuses to compile" mean? I.e. what

On Jan 29, 2010, at 9:42 AM, Wesley Peck wrote: > I have been working on a LLVM backend for the MicroBlaze soft-processor: > http://www.xilinx.com/tools/microblaze.htm > http://en.wikipedia.org/wiki/MicroBlaze Very Cool! > Attached is the initial MicroBlaze patch. It does the following: > 1. Adds mblaze as a target in configure and configure.ac > 2. Adds mblaze specific

On Sep 18, 2008, at 4:04 PM, Villmow, Micah wrote: > I am using lowering instructions and using custom opcodes that I can > more easily directly map to my backend. These opcodes are then used > to emit a custom set of instructions into the MachineBasicBlock. > I’ve been able to get one to work correctly, however, I’ve ran into > an issue where my second one is being

I have been working on a LLVM backend for the MicroBlaze soft-processor: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze Attached is the initial MicroBlaze patch. It does the following: 1. Adds mblaze as a target in configure and configure.ac 2. Adds mblaze specific intrinsics in include/llvm/IntrinsicsMBlaze.td and include/llvm/Intrinsics.td 3. Adds mblaze

> > what does "refuses to compile" mean? I.e. what error do you get? > Specifically I get this message when compiling with the default -mattr: Call result #2 has unhandled type i32 UNREACHABLE executed at CallingConvLower.cpp:162! 0 llc 0x0000000100a1e115 PrintStackTrace(void*) + 38 1 llc 0x0000000100a1e6d0 SignalHandler(int) + 254 2

Hi, I'm implementing __builtin_setjmp and __builtin_longjmp for Sparc 32 bit processors (64 bit later, time allowing). I'm basing the code on the PowerPC version, which itself is based on the X86 version. This code is very nearly working, and I've had it working for -O0 optimisation (with a slightly different version to that below), so I know it's close. However, the PowerPC

I am using lowering instructions and using custom opcodes that I can more easily directly map to my backend. These opcodes are then used to emit a custom set of instructions into the MachineBasicBlock. I've been able to get one to work correctly, however, I've ran into an issue where my second one is being confused as a FRAMEADDR opcode instead of my opcode. DValue

Hi Rafael, > I am trying to add support for select_cc. In ARM it can be implemented > with: > > mov $dst, $falseVal > cmp $a, $b > moveq $dst, $trueVal The more normal ARM code, as produced by assembly writers and compilers that I've seen, is cmp $a, $b moveq $dst, $trueVal movne $dst, $falseVal e.g. at the end of a function returning r0 orr r0, r0, #0x40

I am trying to add support for select_cc. In ARM it can be implemented with: mov $dst, $falseVal cmp $a, $b moveq $dst, $trueVal My current strategy is to expand select_cc in two ARM nodes: ARM::SELECT and ARM::CMP. The two nodes would be connected by a flag edge. ARM::CMP would then expand to "cmp $a, $b". This instruction has no results. It only alters the CPSR (current program

On Mon, Aug 21, 2006 at 05:09:10PM -0300, Rafael Espíndola wrote: > I am trying to add support for select_cc. In ARM it can be implemented > with: [snip] Speaking of new backends, there is a document that lists some architecture docs: http://llvm.org/docs/CompilerWriterInfo.html . There is a link to the GCC library as well, which is rather extensive and may be helpful in writing a new

> If you find any good references to optimization manuals, etc. that > aren't mentioned there, please send them along. In http://www.arm.com/products/DevTools/ABI.html there is a collection of documents regarding the ABI for the ARM architecture. Best Regards, Rafael

someguy wrote: > Hi All, > > I need to implement select_cc as a "cmp; mov rX,1; brcond cnd, END; > mov rX,0; END:" sequence. > > Chris mentioned that the PPC code (as well as the x86 SSE code) does > this, but I can't seem to find it. > > What I really need to kmow is how to insert the branch/label pair at > instruction selection phase. > > Anyone

Let's consider the following piece of C code: (incomplete and not compilable ;) ) result = initValue; for(i) { ... if(condition) result = updatedValue_i; ... } For targets with conditional moves, the result is updated using the following sequence of instructions: regTmp = regFalse; if(condition2) regTmp = regTrue; regResult = regTmp; Now, you have 2 cases: 1)

Hello, I'd like to write some unit tests which verifies SELECT_CC and BR_CC lowering for ARM target, but I'm almost completely unfamiliar with llvm/Target. How can I get this nodes in DAG? Thanks. -- Kind regards, Dmitry Borisenkov -------------- next part -------------- An HTML attachment was scrubbed... URL: