similar to: [LLVMdev] error: instruction requires: thumb2

Displaying 20 results from an estimated 2000 matches similar to: "[LLVMdev] error: instruction requires: thumb2"

2012 Aug 16
0
[LLVMdev] error: instruction requires: thumb2
On Thu, Aug 16, 2012 at 12:55 PM, Lei Zhao <leizhao833 at gmail.com> wrote: > Hi Everybody, > > I recently did a cross-compiling using clang (built with host=x86, target=arm) with the following command: > > > clang -march=armv7-a -mfloat-abi=soft -ccc-host-triple arm-none-linux-gnueabi -integrated-as main.c -o main.o -c > > and get error message: > >
2012 Aug 16
2
[LLVMdev] error: instruction requires: thumb2
It works. But a follow-up question: why do I have to compile it to thumb mode in order to pass the compilation? Is there a way to make it compile to regular arm mode? Thanks. - Lei On Aug 16, 2012, at 4:00 PM, Eli Friedman wrote: > On Thu, Aug 16, 2012 at 12:55 PM, Lei Zhao <leizhao833 at gmail.com> wrote: >> Hi Everybody, >> >> I recently did a cross-compiling
2012 Aug 16
0
[LLVMdev] error: instruction requires: thumb2
Sure. Use legal ARM mode syntax for the instruction. Specifically, there is no offset immediate for the ARM mode LDREX instruction. It's illegal syntax to supply one, even if it's zero. -Jim On Aug 16, 2012, at 2:36 PM, Lei Zhao <leizhao833 at gmail.com> wrote: > It works. But a follow-up question: why do I have to compile it to thumb mode in order to pass the compilation? Is
2015 Apr 30
2
búsqueda y sustitución masiva
Hola a tod en s, explico lo que estoy intentando hacer... Tengo un listado de url comprimidas de twitter, entre las cuales hay muchas repetidas, por lo que el número de registros llega a más de 15K. Por otro lado tengo otra lista de esas url únicas con su equivalente ya descomprimido llegando a un registro de 900. El problema que tengo es que estoy intentando hacer un loop para hacer la
2013 May 08
0
[LLVMdev] Predicated Vector Operations
Jeff Bush <jeffbush001 at gmail.com> writes: > I'm trying to understand how predicated/masked instructions can be > generated in llvm, specifically an instruction where a set bit in the > mask will write the new result into the corresponding vector lane in > the destination and a clear bit will cause the lane in the destination > to remain what it was before the
2013 May 10
4
[LLVMdev] Predicated Vector Operations
Jeff Bush <jeffbush001 at gmail.com> writes: > Ah, I think I get it now. This was mentioned earlier in the thread, > but it didn't click at the time. It sounds like I can do instruction > selection with a pattern like (omitting selection of the sources): > > let Constraints = "$dst = $oldvalue" in { > def MASKEDARITH : MyInstruction< >
2013 May 10
0
[LLVMdev] Predicated Vector Operations
On May 10, 2013, at 11:53 AM, dag at cray.com wrote: > Jeff Bush <jeffbush001 at gmail.com> writes: > >> Ah, I think I get it now. This was mentioned earlier in the thread, >> but it didn't click at the time. It sounds like I can do instruction >> selection with a pattern like (omitting selection of the sources): >> >> let Constraints = "$dst
2013 May 09
2
[LLVMdev] Predicated Vector Operations
On May 9, 2013, at 3:05 PM, Jeff Bush <jeffbush001 at gmail.com> wrote: > On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote: >> Jeff Bush <jeffbush001 at gmail.com> writes: >> >>> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...> >>> %ty = select %mask, %y, <0.0, 0.0, 0.0 ...> >>> %sum = fadd %tx, %ty >>> %newvalue
2013 May 09
0
[LLVMdev] Predicated Vector Operations
On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote: > Jeff Bush <jeffbush001 at gmail.com> writes: > >> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...> >> %ty = select %mask, %y, <0.0, 0.0, 0.0 ...> >> %sum = fadd %tx, %ty >> %newvalue = select %mask, %sum, %oldvalue >> >> I believe the generated instructions depend on whether
2013 May 07
6
[LLVMdev] Predicated Vector Operations
I'm trying to understand how predicated/masked instructions can be generated in llvm, specifically an instruction where a set bit in the mask will write the new result into the corresponding vector lane in the destination and a clear bit will cause the lane in the destination to remain what it was before the instruction executed. I've seen a few places that suggest 'select' is the
2012 Feb 03
2
[LLVMdev] How to properly use copyValue?
Since there are no constructors for Value, how do you properly insert a new Value? If I create a pointer Value *newValue and then call AA.copyValue(oldValue, newValue), this does not work, since newValue is not allocated. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120203/44086cf5/attachment.html>
2012 Feb 04
0
[LLVMdev] How to properly use copyValue?
Ryan Taylor wrote: > Since there are no constructors for Value, how do you properly insert a > new Value? Value is a pure base. If you want to construct a new Value, then you want to construct a global variable or instruction or argument or something in particular. > If I create a pointer Value *newValue and then call > AA.copyValue(oldValue, newValue), this does not work, since
2012 Feb 05
1
[LLVMdev] How to properly use copyValue?
Nick, First, thanks for responding. Secondly, I just want to create an exact copy of an already exisitng Value, this should be pretty simple to do but I'm unclear on how to do this? For example, PHINode::getIncomingValue (unsigned) returns a "Value" and I want to make a copy of that Value. Is there some other way to do this other than copyValue() that I'm missing? On Sat,
2013 May 10
0
[LLVMdev] Predicated Vector Operations
Ah, I think I get it now. This was mentioned earlier in the thread, but it didn't click at the time. It sounds like I can do instruction selection with a pattern like (omitting selection of the sources): let Constraints = "$dst = $oldvalue" in { def MASKEDARITH : MyInstruction< (outs VectorReg:$dst), (ins MaskReg:$mask, VectorReg:$src1, VectorReg:$src2,
2007 Oct 03
4
form_remote_tag :onsubmit not working.
Hi, Has anyone successfully implemented the :onsubmit option for form_remote_tag. It doesn''t seem to work for me. Is there any specific version of rails which is required for the same. Here''s my piece of code. <script> function set_tojid(){ alert(''onsubmit''); } </script> <%= form_remote_tag :update => '''', :url => {
2013 Jan 18
0
[LLVMdev] simple optimization question
Hi Bjorn, > currently the following two lines of code with integer variables get compiled completely differently: > > if (d0<tmp) d0=tmp; there must be something else going on because this void bar(int); void foo(int d0, int tmp) { if (d0 < tmp) d0=tmp; bar(d0); } when compiled like this clang -S -O4 -o - sel.c gives this define void @foo(i32 %d0, i32 %tmp) nounwind
2013 Jan 18
2
[LLVMdev] simple optimization question
Hi, currently the following two lines of code with integer variables get compiled completely differently: if (d0<tmp) d0=tmp; d0 = d0<tmp? tmp : do; The first is compiled into two separate basic blocks, which my backend then optimizes into a conditional move with if-conversion (after instruction selection so not much optimization possible anymore). The second line is compiled into
2013 May 11
0
[LLVMdev] Predicated Vector Operations
On Fri, May 10, 2013 at 9:53 AM, <dag at cray.com> wrote: > Jeff Bush <jeffbush001 at gmail.com> writes: > >> Ah, I think I get it now. This was mentioned earlier in the thread, >> but it didn't click at the time. It sounds like I can do instruction >> selection with a pattern like (omitting selection of the sources): >> >> let Constraints =
2016 May 18
2
LLVM issuse:AArch64 TargetParser
Hi, A64 versus A32/T32 code generation is controlled by the -target option which I don’t believe is under discussion here. James On 18 May 2016, at 13:17, Bruce Hoult <bruce at hoult.org<mailto:bruce at hoult.org>> wrote: Note that armv8a modifies the A32 and T32 instruction sets, and is therefore an important -march option for 32 bit code. Therefore armv8a can not be used to imply
2012 Jul 02
2
[LLVMdev] [PATCH] Apply Thumb2 ROR optimization only when Thumb2 is supported
I've been playing around with using LLVM on one of our projects, which runs on an arm1176jzf-s processor. When compiling for Thumb, a couple of the generated assembly files end up with a 'ror.w' instruction, which is a Thumb2 instruction. Since arm1176jzf-s doesn't support Thumb2, the assembler then turns around and barfs on it. I don't have any experience with this