similar to: [LLVMdev] Casting from float to unsigned char - incorrect output?

> > I didn't realize the code was undefined, I'll let my professor know; but > for code comparison purposes we're still seeking advice on producing the > output that matches the other compilers (even if it involves doing a > translation on the .ll file or additional translation to the produced > assembly). We can't fairly compare the code if it doesn't do the

I'm trying to just emit simple inline assembler (no constraints, inputs, etc.) Can anyone point me to an example of this..? This is corresponding to: __asm__ ("mfc1 $4,$f12"); This is what I tried but it's not correct. std::vector<llvm::Type *> AsmArgTypes; llvm::FunctionType *AsmFTy = llvm::FunctionType::get(Type::getVoidTy(FStub->getContext()),

I'm happy to send you my patch as it stands today. It's not cleaned up yet all or tested thoroughtly but you can look at what I'm doing and maybe suggest some alternate paths and if it's not a matter of redoing everything, I would consider making some changes. Here is a sample stub: Consider this line of code: extern float fpff(float); We have no idea if this is a mips16 or

I'm building a target for the intermediate language of another compiler. The other intermediate language is close to an assembly language (RTL, 1 operation per line), so I based my target off of the Mips target. However, the intermediate language i'm targetting does not support tabs before the instructions. I've looked through the files and found that the tab comes from the

I forgot to mention, the generated file that has the tab is VPOGenAsmWriter.inc. On Sat, Sep 8, 2012 at 2:43 PM, ryan baird <ryanrbaird at gmail.com> wrote: > I'm building a target for the intermediate language of another compiler. > The other intermediate language is close to an assembly language (RTL, 1 > operation per line), so I based my target off of the Mips target.

I'm working on building a target for llvm that's the intermediate language of another compiler, so that the other compiler can benifit from llvm's optimization passes. I essentially made a copy of the mips backend, and then started changing the output to match the intermediate language of the compiler. Most of the output can be overriden, but I haven't figured out how to change

I'm translating llvm's intermediate representation, after optimization, to the intermediate representation of another optimizer. One of the problems I've run into is that llvm sometimes (although rarely) produces strangely sized integers after an opt pass with -O3 (in this example, 832 bits). I need to use 8, 16, or 32 bit integers for the other intermediate language. In short,

Ryan, I've always been bothered by this tab character that doesn't come from the target. The line you're looking for I believe is from /utils/TableGen/AsmWriterEmitter.cpp at line 428. In my opinion the target should control whether a prefix is printed before an instruction. Thanks, Javier From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of ryan

I just accidently sent a partially complete email, so this contains the rest (sorry!) I'm working on translating llvm's optimized intermediate code to another compiler's intermediate code, and I'm working on the PHI instruction. Here's an example phi instruction to help explain what I'm trying to do: %inc25 = phi i32 [ 1, %entry ], [ %inc, %for.body ] What I would want to

2012/9/9 ryan baird <ryanrbaird at gmail.com>: > I'm working on building a target for llvm that's the intermediate language > of another compiler, so that the other compiler can benifit from llvm's > optimization passes. > > I essentially made a copy of the mips backend, and then started changing the > output to match the intermediate language of the compiler.

Esentially, I'm working on a translator someone started building for llvm2.9 that translates an optimized .lln file to another intermediate language, and I'm porting it to 3.1. There is a new intrinsic that pops up in our test cases' lln files that never used to, llvm.lifetime.start. I looked up the description: "The 'llvm.lifetime.start' intrinsic specifies the start of

> It is exactly intended to handle section names as what they are -- > section names. The only reason it works with GCC is because it writes an > assembler stream. +1 Reed, this fails in gcc if you do LTO, no? > Joerg Cheers, Rafael

Is there a pass I can use after reg2mem to get rid of occurances like this?: store i32 %cond, i32* %cond.reg2mem %cond.reload = load i32* %cond.reg2mem store i32 %cond.reload, i32* %cond4.reg2mem Essentially, in this case, reg2mem creates an extra memory space to store and load a value from just here, and never uses the value again; since this isn't efficient code, I'm wondering if

I'm working on a target based on the MIPS target, and when I copy f64 values into 32 bit registers for calling functions, I need the operation to work on a of 32 bit registers (because the language I'm translating to isn't actually mips). I've been looking at how to do this, but I haven't been able to figure it out. Since the Mips target code is still really close to mine,

I was reading about the order of optimizations in the code generation stage here: http://llvm.org/docs/CodeGenerator.html#the-high-level-design-of-the-code-generator This is the part that's interesting to me: 3. SSA-based Machine Code Optimizations<http://llvm.org/docs/CodeGenerator.html#ssa-based-machine-code-optimizations>— This optional stage consists of a series of machine-code

> We also wanted the stubs to be real functions to llvm. That allows them to > participate properly > in optimization of various levels (including LTO). They can even be inlined. > There are other > planned optimizations that would not work if they were not legitimate > functions. I am not saying that the functions should not exist in the IL, just that they should not be inline

I'm working on translating llvm's optimized intermediate code to another compiler's intermediate code, and I'm working on the PHI instruction. Here's an example phi instruction to help explain what I'm trying to do: %inc25 = phi i32 [ 1, %entry ], [ %inc, %for.body ] What I would want to do here is allocate some memory memory (i'm trying to use %phi1 = alloca i32,

On 04/24/2013 03:47 PM, Rafael Espíndola wrote: > On 24 April 2013 18:30, reed kotler <rkotler at mips.com> wrote: >> There are a lot of issues. >> >> For one, the function I'm compiling is a mips16 function but the stubs being >> created are mips32 functions. >> > This looks similar to thumb x 32 bit arm. Wouldn't a similar solution > work for

Ryan, I don't think I fully understand the problem you described, but please see the comments below. Hope this helps you solve the problem. On Sat, Oct 6, 2012 at 3:18 PM, ryan baird <ryanrbaird at gmail.com> wrote: > I'm working on a target based on the MIPS target, and when I copy f64 > values into 32 bit registers for calling functions, I need the operation to > work

This came about in trying to implement some stubs used by gcc mips16 for allowing floating point interoperability with mips32. You get the following looking code from gcc -mips16: # Stub function for foovf (float) .section .mips16.fn.foovf,"ax", at progbits .align 2 .set nomips16 .set nomicromips .ent __fn_stub_foovf .type __fn_stub_foovf, @function __fn_stub_foovf: la