similar to: [LLVMdev] TableGen related question for the Hexagon backend

On Aug 1, 2012, at 1:53 PM, Jyotsna Verma <jverma at codeaurora.org> wrote: > > Currently, we rely on switch tables to transform between formats. However, > we would like to have a different mechanism to represent these relationships > instead of switch tables. I am thinking of modeling these relations in > HexagonInstrInfo.td file and use TableGen to generate a table with

Hi Everyone, After some more thoughts to the Jacob's suggestion of using multiclasses for Opcode mapping, this is what I have come up with. Please take a look at the design below and let me know if you have any suggestions/questions. I have tried to keep the design target independent so that other targets could benefit from it. 1) The idea is to add 3 new classes into

On Aug 16, 2012, at 1:39 PM, Jyotsna Verma <jverma at codeaurora.org> wrote: > Hi Everyone, > > After some more thoughts to the Jacob's suggestion of using multiclasses for > Opcode mapping, this is what I have come up with. Please take a look at the > design below and let me know if you have any suggestions/questions. Hi Jyotsna, You are on to something here, but you

Hi Jacob, Thanks for the suggestions. I have a few questions here. > You are on to something here, but you don't need to define a 'Relations' class > on top of the tablegen records. They are already relations, you just need the > proper query language to match the instructions you want. Are you saying that the mechanism is already present which allows us to relate

Hi, ABCRegister.td : def SGPR32 : RegisterClass<"ABC", [i32], 16, (add S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 )>; def SFGPR32 : RegisterClass<"ABC", [f32], 16, (add S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 )>; ===== Instruction selection ends: ... t8: i32 = ADDrr t37, t32

Hi, I'd like to understand how register allocation works in the case where an instruction is folded into another one. Where in the code would be a good place to start looking at? After ISEL, one of the instructions has another instruction folded into it, which looks like this t1: i32,i1,i1,i1,i1 = ADDRR TargetFrameIndex:i32<0>, MOVRI:i32,i1,i1 But during the 'Assembly

Hello all, I am at the adding Instruction Set stage of adding new target support into LLVM. There is a single instruction op mnemonic with multiple operand forms. For example: Add R1, R2 & Add @R1, R2. I found that there is similar case in x86 instruction set, such like ADD reg, reg & ADD mem, reg. However, the solution of x86 is adding suffix of instruction and translating instruction op

I have this same problem in our backend. I solve it by adding a pseudo instruction at instruction selection that transforms @R1 into R1, so only a single pattern is required. I then can propogate the pseudo instruction after instruction selection. Micah From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Lu Mitnick Sent: Tuesday, January 18, 2011 10:29 AM

Hello Villmow, Is it your backend EFI Byte Code Virtual Machine?? Would you mind to give me an example about what pseudo instruction you add?? thanks a lot yi-hong 2011/1/19 Villmow, Micah <Micah.Villmow at amd.com> > I have this same problem in our backend. I solve it by adding a pseudo > instruction at instruction selection that transforms @R1 into R1, so only a > single

Hello, Im (trying) to write a backend for a simple 32bit processor architecture, with a single instruction format having no condition code registers. www.docm.mmu.ac.uk/STAFF/A.Nisbet/Sabre.pdf is the short 15 page document describing the architecture of Sabre. It is a Celoxica developed research/teaching processor, pages 5-8 contain relevant information for targetting it from a new compiler

I'm writing a back-end for a target in which all dyadic instructions support one register and one memory operand but only some instructions support two register operations. For example ADDrm and ADDrr are supported, ANDrm is supported but ANDrr isn't. I've written descriptions for ADDrm, ADDrr and ANDrm in my InstrInfo.td file but instruction selection fails when presented with an AND

On Aug 17, 2012, at 10:02 AM, "Jyotsna Verma" <jverma at codeaurora.org> wrote: > > Hi Jacob, > > Thanks for the suggestions. I have a few questions here. > >> You are on to something here, but you don't need to define a 'Relations' > class >> on top of the tablegen records. They are already relations, you just need > the >>

Hi, I am experimenting with creating instructions that write into virtual registers that use the ARM GPRPair register class in Pre-RA phase. During register allocation, I hit an assertion because the code is not in SSA form: lib/CodeGen/MachineRegisterInfo.cpp:271: llvm::MachineInstr* llvm::MachineRegisterInfo::getVRegDef(unsigned int) const: Assertion `(I.atEnd() || llvm::next(I) ==

On 25/05/2012 00:40, Sebastian Pop wrote: > On Thu, May 24, 2012 at 5:06 PM, Hal Finkel<hfinkel at anl.gov> wrote: >> Sebastian, >> >> First, it might be useful to look at what is done in the PowerPC >> backend. PPC also has condition registers that are larger than the >> 1-bit conditional results, and it defines 1-bit subregisters in >> addition to

Add an optional parameter to disable this behaviour, so the Curl module in v2v won't print user-sensible data (like passwords). --- builder/checksums.ml | 1 - builder/downloader.ml | 1 - builder/sigchecker.ml | 1 - mllib/common_utils.ml | 4 +++- mllib/common_utils.mli | 7 +++++-- v2v/curl.ml | 2 +- 6 files changed, 9 insertions(+), 7 deletions(-) diff --git

Introduce a new option to control how virt-resize behaves when asking to expand a filesystem, either unknown to libguestfs or that virt-resize cannot expand. The default keeps the current behaviour, i.e. just warn. --- bash/virt-resize | 3 +++ resize/resize.ml | 65 ++++++++++++++++++++++++++++++++++++++++++++++++-- resize/virt-resize.pod | 28 +++++++++++++++++++++- 3 files

Hello LLVM developers, I have a few questions regarding the passes that are run after instruction selection and before register allocation. I am writing a scheduling pass (modulo scheduling). Before I ask my questions, I will first try to explain the approach I am taking. - Currently, I am running the passes in the following order. (-debug-pass=Structure output) Remove unreachable machine

Hi, I’m facing a crash issue (--target=arm-linux-gnueabi -march=armv8-a+crc -mfloat-abi=hard) and debugging the problem, I found that an intended branch was not taken due to bad code generation after the Post RA Scheduler pass. A CMPri instruction after an INLINEASM block (which inturn contains a cmp, bne instruction) is being moved before the INLINEASM block incorrectly resulting in two

Hi Joseph, It's that what I want!! Sequentially, my bad saying random! Well... with the script, I remember I did something like this 15 years ago with qmail with a php script, that every email was saved in mysql and I always selected the next email addrr in the list. Going to search for this option in postfix, thanks for the tip as this is a bit offtopic of dovecot, -----Original

"Villmow, Micah" <Micah.Villmow at amd.com> writes: > I have this same problem in our backend. I solve it by adding a pseudo > instruction at instruction selection that transforms @R1 into R1, so > only a single pattern is required. I then can propogate the pseudo > instruction after instruction selection. What's the rationale behind this approach? It seems a bit