similar to: [LLVMdev] Request for merge: GHC/ARM calling convention.

On Jun 24, 2012, at 7:18 AM, Karel Gardas <karel.gardas at centrum.cz> wrote: > > Hello, > > first of all: one of the LLVM 3.0 new feature was a support for GHC specific calling convention on ARM platform. It looks like this support was merged just into 3.0 branch, specifically it appeared in 3.0 RC2. > Anyway, I hope this is just a mistake or omission that such support was

Hi Karel, I understand this patch has already been merged (to 3.0), so don't take my question as stopping the merge to head, I'm just making sure I got it right... The rest looks correct. + CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, + CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>, + CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22,

Hi Renato, On 06/25/12 12:13 AM, Renato Golin wrote: > Hi Karel, > > I understand this patch has already been merged (to 3.0), so don't > take my question as stopping the merge to head, I'm just making sure I > got it right... The rest looks correct. > > + CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, > + CCIfType<[f64], CCAssignToReg<[D8, D9,

On 29 June 2012 17:46, Karel Gardas <karel.gardas at centrum.cz> wrote: > Yes and no. Shortly: original GHC/ARM/LLVM port was done by Stephen on > ARMv5/Qemu IIRC. I've later added whole VFP support and ARMv7 support. The > code in GHC is properly #ifdefed, so if there is no VFP available on pre > ARMv6, then it's not used. ie. GHC STG floating points regs are then >

Hi Tim, On 01/ 8/14 10:24 PM, Tim Northover wrote: > Hi Karel, > >> I've observed the same issue with LLVM 3.4 as distributed by Ubuntu 13.10 >> and with LLVM HEAD compiled on January 6. I'm able to provide the byte-code >> file which results in this issue, but would first like to know if this is a >> known issue in AArch64 target support or if I shall submit

All, I would like to submit the attached patch, which allows the GHC (Glasgow Haskell Compiler) calling convention to work on ARM targets. Could some nice person please review this code, so I can move towards getting it committed? I have thoroughly tested this patch again GHC on a Debian-ARM (armel) system. Unfortunately my understanding of LLVM is limited, so it's likely I'm not

Hi Steve, I'm not an LLVM developer but am the author/maintainer of the LLVM backend in GHC. The patch looks mostly good to me (although I am not that familiar with ARM so could easily have missed something). My main concern is why are you avoiding using the R0 - R3 registers? Also, could you please update me on the status of this work. I assume you are getting GHC running in registerised

Hi Duncan, > const unsigned* > ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { > + bool ghcCall = false; > + > + if (MF) { > + const Function *F = MF->getFunction(); > + ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false); > + } > This bit looks dubious. Why do you need to do it? What exactly? We need

Hi Duncan, On 10/14/11 03:56 PM, Duncan Sands wrote: > Hi Karel, > >> > const unsigned* >> > ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) >> const { >> > + bool ghcCall = false; >> > + >> > + if (MF) { >> > + const Function *F = MF->getFunction(); >> > + ghcCall = (F ? F->getCallingConv() ==

Hi Karel, >>> > const unsigned* >>> > ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) >>> const { >>> > + bool ghcCall = false; >>> > + >>> > + if (MF) { >>> > + const Function *F = MF->getFunction(); >>> > + ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);

David, Thanks for that - I emailed Karel Gardas. I've got GHC successfully registerised on ARM, and I'm just starting on pushing it upstream. The reason why I'm avoiding the R0-R3 registers is mainly because my qemu-based ARM VM takes days to compile everything, and I was being conservative. The GHC code can call directly out to C, so it would need to save its own R0-R3 when it

Hello, I'm working on implementing GHC specific call convention into LLVM 2.9. I've chosen LLVM 2.9 as a kind of stable reference point and I would like to know how mature is ARM code generation chain inside this release. I've had a hope that perhaps Apple as a main sponsor of LLVM is using LLVM for their ARM based iOS software development, but I'm not sure if I'm right

Hi Karel, > > const unsigned* > > ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { > > + bool ghcCall = false; > > + > > + if (MF) { > > + const Function *F = MF->getFunction(); > > + ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false); > > + } > > > This bit looks dubious. Why do you

Hello, today is the last day[1] when someone might ask for feature merge into the LLVM 3.0 release. I'd like to ask you to merge attached patch. This is implementation of GHC calling convention on ARM platform which is made by Stephen Blackheath with few additions by me. I hope that although the patch does not contain any test case, it still will be merged. The reason for this is that

I don't know if GuaranteedTailCallOpt is in anyone's plans. It might be a good idea to implement some time. I am not sure what GHC's exact needs are, though. Cameron On Jun 17, 2011, at 1:49 PM, Karel Gardas wrote: > > Hello Cameron, > > thanks a lot for your fast answer, which just makes me curious if making ARM tailcalls on par with x86 in the future is on some of

Hello Cameron, thanks a lot for your fast answer, which just makes me curious if making ARM tailcalls on par with x86 in the future is on some of the development plans already? If not, then what do you think is the complexity of such work? Thanks! Karel On 06/17/11 10:41 PM, Cameron Zwarich wrote: > They work pretty well now, at least on Thumb2 / Darwin. It is still fairly conservative

On Jun 16, 2011, at 1:35 PM, Karel Gardas wrote: > I'm working on implementing GHC specific call convention into LLVM 2.9. I've chosen LLVM 2.9 as a kind of stable reference point and I would like to know how mature is ARM code generation chain inside this release. I've had a hope that perhaps Apple as a main sponsor of LLVM is using LLVM for their ARM based iOS software

On 06/16/11 11:00 PM, John McCall wrote: > On Jun 16, 2011, at 1:35 PM, Karel Gardas wrote: >> I'm working on implementing GHC specific call convention into LLVM >> 2.9. I've chosen LLVM 2.9 as a kind of stable reference point and I >> would like to know how mature is ARM code generation chain inside >> this release. I've had a hope that perhaps Apple as a

Attached is a prototype patch that uses CCState to lower RET nodes in the ARM target. Lowering CALL nodes will come later. This patch does not handle f64 and i64 types. For these types, it would be ideal to request the conversions below: def RetCC_ARM_APCS : CallingConv<[ CCIfType<[f32], CCBitConvertToType<i32>>, CCIfType<[f64], CCBitConvertToType<i64>>,

Hi, all On the website, it says, CCAssignToRegWithShadow <registerList, shadowList> — similar to CCAssignToReg, but with a shadow list of registers I don't know when we should use CCAssignToRegWithShadow. Because I am not a architecture expert, please bear with my naive question. Take ARMCallingConv.td as an example, CCIfType<[i32], CCIfAlign<"8",