Displaying 20 results from an estimated 10000 matches similar to: "[LLVMdev] Last use of operand within BasicBlock?"
2012 Jul 25
1
[LLVMdev] Inneffiecient code produced by reg2mem?
Is there a pass I can use after reg2mem to get rid of occurances like this?:
store i32 %cond, i32* %cond.reg2mem
%cond.reload = load i32* %cond.reg2mem
store i32 %cond.reload, i32* %cond4.reg2mem
Essentially, in this case, reg2mem creates an extra memory space to store
and load a value from just here, and never uses the value again; since this
isn't efficient code, I'm wondering if
2011 Jun 20
2
[LLVMdev] run -mem2reg and -reg2mem programmably from within a Pass
I am currently building a BasicBlock pass which requires to run -reg2mem
before it, and need to run -mem2reg after it to clean up.
So, I want to specify -reg2mem as one of the pre-requisite passes to it, as:
class MyPass: public BasicBlockPass{
virtual void getAnalysisUsage(AnalysisUsage &AU){
...
AU.addRequired<RegToMem>();
...
}
};
I searched all passes under
2011 Jun 20
0
[LLVMdev] run -mem2reg and -reg2mem programmably from within a Pass
I guess AU.addRequiredID(DemoteRegisterToMemoryID) would do the trick.
- xi
On Jun 19, 2011, at 11:03 PM, Chuck Zhao wrote:
> I am currently building a BasicBlock pass which requires to run -reg2mem before it, and need to run -mem2reg after it to clean up.
>
> So, I want to specify -reg2mem as one of the pre-requisite passes to it, as:
>
>
> class MyPass: public
2010 Oct 12
1
[LLVMdev] Specify dominator for BasicBlock to avoid "Instruction does not dominate all uses!"
Hi, I tried adding the PHI nodes in BB_unique, and it works for the simple
case described here, but in case the nodes were declared in some
predecessors of ExitBB1 and used in ExitBB1_redirect and its successors, it
won't work, unless I create entries for all of them in BB_unique.
B1 (declares PHI_1) B3
| |
B2
2012 May 11
2
[LLVMdev] TableGen pattern for negated operand
I've been unable to come up with the TableGen recipe to match a
negated operand. My target asm syntax allows the following transform:
FNEG r8, r5
MUL r6, r8, r9
to
MUL r6, -r5, r9
Is there a Pattern<> syntax that would allow matching *any* opcode (or
even some subset), not just MUL, with a FNEG'd operand? I expect I can
define a PatFrag:
def fneg_su : PatFrag<(ops
2005 Nov 22
0
[LLVMdev] Cloning BasicBlock
On Tue, 2005-11-22 at 09:12 -0800, Sandra Johnson wrote:
> Hi ,
> I am trying to clone a BasicBlock. I want both to co-exist and I have
> introduced
> a conditional branch to the original or the cloned BB.
I have a pass I haven't commited that does just this. Well, it does so
to implement Arnold and Ryder style profiling. I can send you a copy of
that if you want (I hope to
2012 Jul 18
2
[LLVMdev] Phi translation
I just accidently sent a partially complete email, so this contains the
rest (sorry!)
I'm working on translating llvm's optimized intermediate code to another
compiler's intermediate code, and I'm working on the PHI instruction.
Here's an example phi instruction to help explain what I'm trying to do:
%inc25 = phi i32 [ 1, %entry ], [ %inc, %for.body ]
What I would want to
2010 Oct 20
0
[LLVMdev] Pass Incompatibility
On 10/20/10 6:05 AM, Luke Dalessandro wrote:
> I have a transformation where I'd like to use both DominatorTree (for ExtractCodeRegion), and DemoteRegisterToMemory (i.e., reg2mem). The transformation is phased, so all occurrences of getAnalysis<DominatorTree>(Function) happen before any occurrence of getAnalysisID<FunctionPass>(&DemoteRegisterToMemoryID, Function).
I
2012 May 11
0
[LLVMdev] TableGen pattern for negated operand
Hi Joe,
Le 11/05/2012 02:13, Joe Matarazzo a écrit :
> I've been unable to come up with the TableGen recipe to match a
> negated operand. My target asm syntax allows the following transform:
>
> FNEG r8, r5
> MUL r6, r8, r9
>
> to
>
> MUL r6, -r5, r9
>
> Is there a Pattern<> syntax that would allow matching *any* opcode (or
> even some
2008 Dec 09
1
[LLVMdev] scalar-evolution + indvars fail to get the loop trip count?
Hi,
Seems pass scalar-evolution+indvars fail to get the loop trip count of the
following case:
int foo(int x, int y, int lam[256], int alp[256]) {
int i;
int z = y;
for (i = 255; i >= 0; i--) {
z += x;
lam[i] = alp[i];
}
return z;
}
The final optimized ll code is :
define i32 @foo(i32 %x, i32 %y, i32* %lam, i32* %alp) nounwind {
entry:
br label %bb
bb:
2005 Nov 23
1
[LLVMdev] Cloning BasicBlock
Hello Andrew ,
Yes , I have missed the phi node since my paths merge together. I'll try this out.
I am implementing a timer based profiling scheme and hope your code will be useful
for me. Please send me a copy of your code.
Thanks
Sandra
Andrew Lenharth <andrewl at lenharth.org> wrote: On Tue, 2005-11-22 at 09:12 -0800, Sandra Johnson wrote:
> Hi ,
> I am trying
2012 Jul 18
1
[LLVMdev] (no subject)
I'm working on translating llvm's optimized intermediate code to another
compiler's intermediate code, and I'm working on the PHI instruction.
Here's an example phi instruction to help explain what I'm trying to do:
%inc25 = phi i32 [ 1, %entry ], [ %inc, %for.body ]
What I would want to do here is allocate some memory memory (i'm trying to
use %phi1 = alloca i32,
2010 Oct 20
5
[LLVMdev] Pass Incompatibility
I have a transformation where I'd like to use both DominatorTree (for ExtractCodeRegion), and DemoteRegisterToMemory (i.e., reg2mem). The transformation is phased, so all occurrences of getAnalysis<DominatorTree>(Function) happen before any occurrence of getAnalysisID<FunctionPass>(&DemoteRegisterToMemoryID, Function).
If I register these two passes with DominatorTree first, I
2008 Jul 12
3
[LLVMdev] Little bug in LoopInfo after Rotate?
Hello, I have two for loops (one inside the other), that after indvars,
looprotate, etc. (the important here is the loop rotate), is similar to this
(I've stripped the real operations):
define i32 @f() nounwind {
entry:
br label %bb1
bb1: ; preds = %bb3, %bb1, %entry
%i.0.reg2mem.0.ph = phi i32 [ 0, %entry ], [ %i.0.reg2mem.0.ph, %bb1 ],
[ %indvar.next9, %bb3 ] ;
2010 Apr 20
2
[LLVMdev] How to delete a instruction?
Hi,
when I delete some instruction, I got some error prompt message.
- %i.0.reg2mem.0 = phi i32 [ 0, %bb5 ], [ %indvar.next, %bb12 ] ; <i32>
[#uses=2]
- %s.0.reg2mem.0 = phi i32 [ 0, %bb5 ], [ %tmp16, %bb12 ] ; <i32> [#uses=1]
- %tmp14 = tail call i32 @foobar(i32 %i.0.reg2mem.0) nounwind ; <i32>
[#uses=1]
- %tmp16 = add i32 %tmp14, %s.0.reg2mem.0 ; <i32>
2011 Aug 03
0
[LLVMdev] scalar evolution to determine access functions in arays
On 08/03/2011 08:35 AM, Jimborean Alexandra wrote:
> Hello Tobi,
>
> You are right, we need to run some other passes before running the
> scalar evolution pass. The sequence that I run for this example is -O3
> -loop-simplify -reg2mem. This is why I did not obtain the expressions
> depending on the loop indices. So I removed the reg2mem pass and scalar
> evolution computes the
2011 Aug 03
2
[LLVMdev] scalar evolution to determine access functions in arays
Hello Tobi,
You are right, we need to run some other passes before running the scalar evolution pass. The sequence that I run for this example is -O3 -loop-simplify -reg2mem. This is why I did not obtain the expressions depending on the loop indices. So I removed the reg2mem pass and scalar evolution computes the correct functions.
However, I need to run the reg2mem pass (or any other that
2005 Nov 22
3
[LLVMdev] Cloning BasicBlock
Hi ,
I am trying to clone a BasicBlock. I want both to co-exist and I have introduced
a conditional branch to the original or the cloned BB.
I tried mapping the original instruction and the clone as below :
Instruction *NewInst = II->clone();
if (II->hasName())
NewInst->setName(II->getName());
NewBB->getInstList().push_back(NewInst);
ValueMap[II] =
2011 May 17
1
[LLVMdev] eliminate phi nodes, reduce unnecessary loads / stores , reg2mem, mem2reg
Hi,
I work on a pass that requires as input LLVM code without any phi nodes. For
this, I use the reg2mem pass which produces suitable code, the pass runs
correctly, but I obtain a significant performance decrease. I expect that this
is because there are more reads / writes to memory after running the reg2mem
pass.
How can I optimize the code, without inserting any phi nodes? Or is there a
2010 Oct 11
0
[LLVMdev] Specify dominator for BasicBlock to avoid "Instruction does not dominate all uses!"
On Oct 11, 2010, at 9:05 AM, Xinfinity wrote:
>
> Hi,
>
> I am working on a pass aimed to unify multiple exits of a loop into a unique
> basic block. The approach is straight forward:
> I create a unique BasicBlock BB_unique that has as predecessors all the exit
> blocks of the loop, it contains a phi instruction and a switch to redirect
> the flow correctly.