similar to: [LLVMdev] Issue with Machine Verifier and earlyclobber

Displaying 20 results from an estimated 500 matches similar to: "[LLVMdev] Issue with Machine Verifier and earlyclobber"

2012 Jul 14
0
[LLVMdev] Issue with Machine Verifier and earlyclobber
On Jul 14, 2012, at 10:09 AM, Borja Ferrer <borja.ferav at gmail.com> wrote: > Hello, > > I'm getting a machine verifier error after introducing the earlyclobber constraint to some instructions where the src and dest regs can't be the same. The offending instruction pattern is this one: > > let canFoldAsLoad = 1, > isReMaterializable = 1, > Constraints =
2012 Jul 14
2
[LLVMdev] Issue with Machine Verifier and earlyclobber
Hello Jakob, I'm still getting the error, I can give you any other debug info you need. I haven't pasted the regalloc debug info here because it is quite huge, but if you tell me what specific details you need I will include them. Thanks for your help! 2012/7/14 Jakob Stoklund Olesen <stoklund at 2pi.dk> > > On Jul 14, 2012, at 10:09 AM, Borja Ferrer <borja.ferav at
2012 Jul 15
0
[LLVMdev] Issue with Machine Verifier and earlyclobber
Jakob, one more hint, I've placed some asserts around the code you added and noticed that the InlineSpiller::insertReload() function is not being called. 2012/7/14 Borja Ferrer <borja.ferav at gmail.com> > Hello Jakob, > > I'm still getting the error, I can give you any other debug info you need. > I haven't pasted the regalloc debug info here because it is quite
2017 May 28
2
Pseudo-instruction that overwrites its input register
Hi, I'd like to define a pseudo-instruction whose expansion will, as a side-effect, overwrite an input register's value: the pseudo-instruction ldw r1:r2, P to load 2 bytes from memory address P is to be expaneded to ld r1, P+ ld r2, P where "ld _, P+" is an instruction that loads a single byte from P, and post-increments P by one. How can I represent this behaviour in
2019 Mar 11
3
IsDead, IsKill
Thanks. I saw the header comments but it wasn’t clear to me what the difference between those concepts is? My slightly vague understanding is IsDef means that the register specified by this operand is set by the machine instruction. So I understand that to mean the MO will override that register? Also things like early clobber, perhaps there is another document that clarifies some of these
2017 May 28
2
Pseudo-instruction that overwrites its input register
On Sun, 28 May 2017, David Chisnall wrote: >> let Constraints = "@earlyclobber $reg" in >> def LDWRdPtr : Pseudo<(outs DREGS:$reg), >> (ins PTRREGS:$ptrreg), >> "ldw\t$reg, $ptrreg", >> [(set i16:$reg, (load i16:$ptrreg))]>, >>
2020 May 05
2
"Earlyclobber" but for a subset of the inputs
Hi Quentin, > It sounds like you only need the earlyclobber description for the N, N > variant. > In other words, as long as you use different opcodes for widen-op NN and > widen-op WN, you model exactly what you want. > > What am I missing? > we are using different opcodes for widen-op NN and widen-op WN. My understanding is that not setting earlyclobber to the W, N
2020 May 04
2
"Earlyclobber" but for a subset of the inputs
Hi all, I'm working on a target whose registers have equal-sized subregisters and all of those subregisters can be named (or the other way round: registers can be grouped into super registers). So for instance we've got 16 registers W (as in wide) W0..W15 and 32 registers N (as in narrow) N0..N31. This way, W0 is made by grouping N0 and N1, W1 is N2 and N3, W2 is N4 and N5, ..., W15 is
2012 Jul 15
2
[LLVMdev] Issue with Machine Verifier and earlyclobber
On Jul 15, 2012, at 9:20 AM, Borja Ferrer <borja.ferav at gmail.com> wrote: > Jakob, one more hint, I've placed some asserts around the code you added and noticed that the InlineSpiller::insertReload() function is not being called. > > 2012/7/14 Borja Ferrer <borja.ferav at gmail.com> > Hello Jakob, > > I'm still getting the error, I can give you any other
2011 Apr 26
2
[LLVMdev] Symbol folding with MC
Hello Jim thanks for the reply, For normal additions with immediates I've done the same as ARM does, basically transforming add(x, imm) nodes to sub(x, -imm) with a pattern in the .td file like this: def : Pat<(add DLDREGS:$src1, imm:$src2), (SUBIWRdK DLDREGS:$src1, (imm16_neg_XFORM imm:$src2))>; Now, the typical pattern concerning additions with global addresses looks
2012 Jul 16
1
[LLVMdev] Issue with Machine Verifier and earlyclobber
On Jul 15, 2012, at 4:50 PM, Borja Ferrer <borja.ferav at gmail.com> wrote: > I think I'm getting a bit closer to the problem. I've found that the call to InlineSpiller::foldMemoryOperand() inside InlineSpiller::spillAroundUses() is causing the problems. > As a test, I removed that call and with your yesterday's patch I'm not getting any errors at all, the code
2012 Jul 15
0
[LLVMdev] Issue with Machine Verifier and earlyclobber
I think I'm getting a bit closer to the problem. I've found that the call to InlineSpiller::foldMemoryOperand() inside InlineSpiller::spillAroundUses() is causing the problems. As a test, I removed that call and with your yesterday's patch I'm not getting any errors at all, the code generated is the same one as with the call. This is happening when
2012 Dec 17
2
[LLVMdev] LLVM ERROR: ran out of registers during register allocation
Hello, I'm getting the "LLVM ERROR: ran out of registers during register allocation" error message for an out of tree target I'm developing. This is happening for the following piece of C code: struct ss { int a; int b; int c; }; void loop(struct ss *x, struct ss **y, int z) { int i; for (i=0; i<z; ++i) { x->c += y[i]->b; } } The problem relies in
2011 Apr 26
0
[LLVMdev] Symbol folding with MC
On Apr 26, 2011, at 1:27 PM, Borja Ferrer wrote: > Hello Jim thanks for the reply, > > For normal additions with immediates I've done the same as ARM does, basically transforming add(x, imm) nodes to sub(x, -imm) with a pattern in the .td file like this: > def : Pat<(add DLDREGS:$src1, imm:$src2), > (SUBIWRdK DLDREGS:$src1, (imm16_neg_XFORM imm:$src2))>;
2011 Apr 27
1
[LLVMdev] Symbol folding with MC
Thanks Jim, I've implemented the negation part successfully :) maybe the second part could be a possible feature request so others could use it aswell? 2011/4/27 Jim Grosbach <grosbach at apple.com> > > On Apr 26, 2011, at 1:27 PM, Borja Ferrer wrote: > > > Hello Jim thanks for the reply, > > > > For normal additions with immediates I've done the same as
2009 Dec 16
2
[LLVMdev] Early-clobber constraint in TableGen
On Dec 15, 2009, at 5:08 PM, David Greene wrote: > On Tuesday 15 December 2009 18:01, Jim Grosbach wrote: > >> For a usage example, I've included in the patch the modification to >> use the constraint for the STREX ARM instruction. > > Your example is: > > constraints = "@early $success" > > Why not spell it as: > > constraints =
2013 Jul 16
3
[LLVMdev] Operand constrain specification
Hi, How can I specify in a .td file that source and destination should not use the same register? Thanks. - Elena --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If
2009 Dec 16
0
[LLVMdev] Early-clobber constraint in TableGen
On Tuesday 15 December 2009 19:52, Jim Grosbach wrote: > Do you have specific examples in mind that would be expressible with > something more complicated that aren't handleable via an early-clobber > constraint? Not offhand, no. I'm mostly concerned about the readability of .td files. > Perhaps spelling it out more fully with "earlyclobber" rather than >
2014 Feb 19
2
[LLVMdev] How to implement register allocation constraints to guide allocator dispatching different registers for certain instruction?
Hi, To fix this bug(http://llvm.org/bugs/show_bug.cgi?id=18881), we need to add more register constraints that for STLXR , Ws and Wt should not be the same register. Because these unpredictable instructions are valid instructions in MC layer, we couldn't just simply treat them as unallocated encoding. I suppose to add some extra rules on register allocator to avoid it allocating register
2011 Mar 25
2
[LLVMdev] Possible missed optimization?
Hello, I've noticed the following issue while testing some codegen tests, i would like to know if it's a missed optimization or i missed something out here. This is for an out of tree backend im writing. I managed to reduce it to the following C function: void foo(int *a) // int here is 16bits { *a &= 0xFF; } This is the code before regalloc: Live Ins: %R25R24