similar to: [LLVMdev] Removing the separation between opt and codegen?

Hi Craig, Thank you very much for your answer. I did not want to discuss exactly the semantic and name of one operation but instead raise the question "would it be beneficial to have more vector builtins?". You wrote that the compiler will recognize a pattern and replace it by __builtin_ia32_haddps when possible, but how can I be sure of that? I would have to disassemble the generated

This patch synthesizes haddps/haddpd/hsubps/hsubpd instructions from floating point additions and subtractions of appropriate vector shuffles. To do this I introduced new x86 FHADD and FHSUB opcodes. These need to be wired up somehow in the .td file to the appropriate instructions. Since I have no idea how tablegen works I just hacked it in horribly. It works, but breaks support for the hadd

> Regarding TLI. So, DAGCombine, CodeGenPrepare, LoopReduce all use the TLI > interface which can answer questions such as "is this operation supported ?" > or "is this type legal". This is a subset of what we need in a vectorized. > We can discuss other requirements that the vectorizer may have after we > finish with the first phase. I suspect that we may

Hi Eric, On Oct 5, 2012, at 11:29 AM, Eric Christopher <echristo at gmail.com> wrote: >> Regarding TLI. So, DAGCombine, CodeGenPrepare, LoopReduce all use the TLI >> interface which can answer questions such as "is this operation supported ?" >> or "is this type legal". This is a subset of what we need in a vectorized. >> We can discuss other

Hi Bruno, > Some comments: > > + // Try to synthesize horizontal adds from adds of shuffles. > + if (((Subtarget->hasSSE3()&& (VT == MVT::v4f32 || VT == MVT::v2f64)) || > + (Subtarget->hasAVX()&& (VT == MVT::v8f32 || VT == MVT::v4f64)))&& > + isHorizontalBinOp(LHS, RHS, true)) > > 1) You probably want to do something like: >

Hi Duncan, On Wed, Sep 21, 2011 at 1:24 PM, Duncan Sands <baldrick at free.fr> wrote: > This patch synthesizes haddps/haddpd/hsubps/hsubpd instructions from > floating > point additions and subtractions of appropriate vector shuffles.  To do this > I > introduced new x86 FHADD and FHSUB opcodes.  These need to be wired up > somehow > in the .td file to the appropriate

Hi, I love llvm vectors, yet I wonder why some advanced vector operations are specific to some CPU targets? Let me take an example: /// Horizontally adds the adjacent pairs of values contained in two /// 128-bit vectors of [4 x float]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> VHADDPS </c> instruction. /// /// \param __a /// A

On Oct 5, 2012, at 12:08 AM, Nick Lewycky <nicholas at mxc.ca> wrote: > I absolutely think that we should have something like TargetData (now DataLayout) but for the vector types and operations. However, I'm not familiar with "Target Lowering Interface". Could you explain? I agree. Once we make the codegen accessible to the IR-level passes we need to start talking about

The output of the avx-hadd program is 3 11 7 15 Preston -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Duncan Sands Sent: Thursday, September 22, 2011 3:14 PM To: Bruno Cardoso Lopes Cc: LLVMdev Subject: Re: [LLVMdev] Patch to synthesize x86 hadd instructions; need help with the tablegen bits Hi Bruno, > Some comments:

Dear all, I am Raghesh, a student pursuing M.Tech at Indian Institute of Technology, Madras, India. I would like to make contribution to the Polly project (http://wiki.llvm.org/Polyhedral_optimization_framework) as part of GSOC 2011. I have gained some experience working in OpenMP Code generation for Polly. This is almost stable now and planning to test with the polybench benchmarks. Some of

>I think that the first step would be to expose Target Lowering Interface (TLI) to OPT's IR-level passes. By "lowering", we assume the bitcode is more abstract than the machine code. However, in some situations, it is just opposite. For instance, some architectures support vectorization of min/max/saturated-{add,sub)/conditional-assignment/etc/../etc. We need to detect such

Hi all, I have run a (glm) analysis where the dependent variable is the gender (family=binomial) and the predictors are percentages. I get a warning saying "fitted probabilities numerically 0 or 1 occurred" that is indicating that quasi-separation or separation is occurring. This makes sense given that one of these predictors have a very influential effect that is depending on a

I have an application I intend to use Opus for that involves creating recordings of two-party conversations where each party is saved as a separate channel. Audio may be later processed or analyzed on a per-party basis so if audio in one channel affects the other channel, it could create problems. My question is, if I use a single stereo Opus stream, how well will channel separation be maintained?

Does someone understand this? I do not. Niels. ----- Forwarded message from laurent Protois <protois at ensea.fr> ----- Subject: NVIDIA and Privilege Separation From: laurent Protois <protois at ensea.fr> To: provos at citi.umich.edu X-Mailer: Ximian Evolution 1.0.7-1mdk Date: 10 Jul 2002 09:29:45 +0200 Hi Niels, i have a little problem with openssh 3.4 and Nvidia kernel driver:

Dear all, I am using R 2.9.2 on Windows XP. I am undertaking a simulation study to consider methods of external validation in the context of missing covariates in the validation data set. I would like to use Royston's measure of prognostic separation as a method of external validation. Although there is no R code for this, the author informs me that it should be easy: 1. Calculate the

>On 11/20/2013 03:37 PM, O'Connor, Kevin wrote: >> I have an application I intend to use Opus for that involves creating > recordings of two-party conversations where each party is saved as a >> separate channel. Audio may be later processed or analyzed on a >> per-party basis so if audio in one channel affects the other channel, >> it could create problems.

Is this a known problem? Niels. ----- Forwarded message from Judah Levine <jlevine at utcnist.colorado.edu> ----- Date: Fri, 5 Jul 2002 08:58:46 -0600 (MDT) From: Judah Levine <jlevine at utcnist.colorado.edu> To: provos at citi.umich.edu Subject: Privilege separation Hello, I have just installed openssh-3.4p1 on a COMPAQ/DEC/HP Alpha running True64 UNIX v4.0F. The privilege

Hello all, I have a question about the design of the privilege separation aspect of openSSH. From what I understand, the interface between the privileged process and the unprivileged one is implemented as a set of well-defined operations with only a small subset of these operations enabled at any given time. These operations are enabled and disabled depending on the task at hand. What I am

Package: libblktapctl0 Severity: minor Dear Maintainer, in DDTSS I see: **** coalescing of differencing disks. . Libvhd is a **** note the extra space before the dot '.' used as paragraph separation Ciao Davide -- Dizionari: http://linguistico.sourceforge.net/wiki Database: http://www.postgresql.org GNU/Linux User: 302090: http://counter.li.org Non autorizzo la memorizzazione del

In https://stat.ethz.ch/pipermail/r-help/2008-March/156868.html I found what linear separability means. But what can I do if I find such a situation in my data? Field (2005) suggest to reduce the number of predictors or increase the number of cases. But I am not sure whether I can, as an alternative, take the findings from my analysis and report them. And if so, how can I find the linear