similar to: [LLVMdev] mapping a virtual register to a specific address

On Fri, Jun 22, 2012 at 2:46 PM, amruth.rd <amruth.rd at knights.ucf.edu>wrote: > > Does LLVM allow mapping a virtual register to a specific memory location? > If not, how do we extract information on where the virtual registers are > mapped to? > In general, you do not know where a virtual register is mapped, and the mapping is dependent on the back-end. It could be

On Fri, Jun 22, 2012 at 3:16 PM, amruth.rd <amruth.rd at knights.ucf.edu>wrote: > Thanks Justin. It was really helpful. > > Can i use "alloca" instruction to allocate memory at a particular address > in the stack? Is it possible to do that? As far as I know, alloca does not > take any address as an operand. > The only control alloca gives you over the address is

Hi Amruth, If you do not specify any optimization flag for 'clang' and do not run 'opt -mem2reg' pass on the generated IR file, it is in non-SSA form. However, many variables stay in memory instead of registers in this case. Thanks, Jiesheng On Wed, Jun 13, 2012 at 1:17 PM, <amruth.rd at knights.ucf.edu> wrote: > I am experimenting with LLVM optimizer and found that

I am experimenting with LLVM optimizer and found that the bit code file clang emits is already in SSA form, but I want to generate it in non-SSA form. Would you let me know if there is any way of doing it? Cheera,Amruth -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hello everyone, I didn't come across mov or copy in LLVM IR instruction set. So what is the best way to move/copy values between virtual registers? Thanks,Amruth -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120607/76fbe6e3/attachment.html>

Well, it *is* in SSA form, but it "cheats" by keeping values in memory. --Sean Silva On Wed, Jun 13, 2012 at 2:00 PM, Jiesheng Wei <jwei at ece.ubc.ca> wrote: > Hi Amruth, > > If you do not specify any optimization flag for 'clang' and do not run > 'opt -mem2reg' pass on the generated IR file, it is in non-SSA form. > However, many variables stay

Hello everyone, I am a newbie to LLVM and I am trying to develop an LLVM pass. I came across this page "Writing an LLVM Pass" which said, "First, configure and build LLVM. This needs to be done directly inside the LLVM source tree rather than in a separate objects directory. " where as LLVM installation page says to have a separate build directory for putting all the binaries.

Hi Tim, Thank you for the quick response! so you'd probably check you're looking at a BranchInst and check BI->getSuccessor(0)->getName() (& 1 if it's conditional) I initially was printing out the result from getName() (I.getParent()->getName()) and it printed out nothing sadly. when parsing the instructions in SelectionDAGBuilder but it was only visiting instructions in

On 6/26/12 5:07 PM, amruth.rd wrote: > Hello, > > I am curious to know if LLVM offers any passes to do interprocedural slicing, I need to eliminate most of the computations(possibly all, if they don't influence the control flow), but the control flow of the program should be maintained at all cost. I did see an optimization pass to print the CFG of a function without its body to a

Hello, I am curious to know if LLVM offers any passes to do interprocedural slicing, I need to eliminate most of the computations(possibly all, if they don't influence the control flow), but the control flow of the program should be maintained at all cost. I did see an optimization pass to print the CFG of a function without its body to a dot file, but I am interested in generating the

Hello Everyone, Would you please send me any links to documentation on LLVM stack? I am particularly interested in knowing how each instruction in an LLVM bit code file(.ll file) affects its stack. To be specific, is it possible to map an LLVM program as operations on a stack? Thanks, Amruth

It is my understanding that all you need to do is specify let isTarget = 1 in your .td file and it will generate target specific intrinsics. This should allow you to keep the IntrinsicsPTX.td file in the same location. Micah From: Justin Holewinski [mailto:justin.holewinski at gmail.com] Sent: Monday, December 05, 2011 6:13 AM To: Alberto Magni Cc: Villmow, Micah; LLVM Developers Mailing List

I'm curious about the design rationale for how ManagedStatic instances are cleaned up, and I'm hoping someone can shed some light on it. Currently, ManagedStatic objects are cleaned up when llvm_shutdown() traverses the global list of initialized objects and calls destroy() on each. This leads to two questions: 1. An assertion enforces that the objects are deleted in reverse order of

Hi, We've recently encountered a problem in our compiler where the line number in debug info jumps back and force even at O0. This is caused by DAG node ordering not being properly kept during legalization and instruction selection. There are still uncaught cases after applying the patch mentioned here. So I have decided to implement the approach suggested by Andy as below. i.e. maintain the

Hi Justin, sorry for the delay, I have been busy. Micah's proposal requires to move the definitions of the intrinsics from include/llvm/IntrinsicsPTX.td to lib/Target/PTX/PTXIntrinsics.td thus allowing the generation of the file PTXGenIntrinsics.inc which will be included by PTXIntrinsicInfo.cpp. This is a quite big modification, do you agree with this ? Or do you have a better solution.

----- Original Message ----- > From: dag at cray.com > To: "Justin Holewinski" <justin.holewinski at gmail.com> > Cc: "Hal Finkel" <hfinkel at anl.gov>, "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> > Sent: Friday, January 11, 2013 2:13:50 PM > Subject: Re: [LLVMdev] Documentation of fmuladd intrinsic > > Justin

On Thu, Dec 8, 2011 at 11:36 AM, Villmow, Micah <Micah.Villmow at amd.com>wrote: > It is my understanding that all you need to do is specify let isTarget = > 1 in your .td file and it will generate target specific intrinsics. This > should allow you to keep the IntrinsicsPTX.td file in the same location. > So we keep the intrinsics defined in include/llvm/IntrinsicsPTX.td?

Yes, total number of PTX registers that will be emitted is exactly what I need. It's hard to figure out this in LLVM IR level. 2013/8/7 Justin Holewinski <justin.holewinski at gmail.com> > Is there any way you could approximate the register/instruction usage and > perform live-range analysis in a higher-level LLVM IR pass? I'm not sure > how useful NVPTXRegisterInfo

On 29 September 2011 13:54, Justin Holewinski <justin.holewinski at gmail.com> wrote: > Did you try to re-run configure after pulling that commit? > I just tried a shared build with: > ../configure --enable-optimized --enable-assertions > --enable-targets=host,ptx --enable-shared > And the build is successful. > What is your configure line, and system OS? Not sure it's

On Mon, Nov 21, 2011 at 11:45 AM, Alberto Magni <alberto.magni86 at gmail.com>wrote: > On Mon, Nov 21, 2011 at 3:36 PM, Justin Holewinski > <justin.holewinski at gmail.com> wrote: > > On Mon, Nov 21, 2011 at 7:01 AM, Alberto Magni < > alberto.magni86 at gmail.com> > > wrote: > >> > >> Hi Justin, > >> > >> attached you find