similar to: [LLVMdev] Post-RA Def/Use Information

On Jun 15, 2012, at 2:54 PM, dag at cray.com wrote: > Looking through TOT sources, I don't see anything that would provide > def/use chains (or equivalent information) post register allocation. I > would like to write some peeps to clean up various target-specific > things but for safety I will need such information. > > Is such an analysis pass available somewhere that

On 6/15/2012 6:00 PM, Owen Anderson wrote: > On Jun 15, 2012, at 2:54 PM, dag at cray.com wrote: > >> Looking through TOT sources, I don't see anything that would provide >> def/use chains (or equivalent information) post register allocation. I >> would like to write some peeps to clean up various target-specific >> things but for safety I will need such

On Jun 15, 2012, at 3:07 PM, Joshua Cranmer <pidgeot18 at gmail.com> wrote: > On 6/15/2012 6:00 PM, Owen Anderson wrote: >> On Jun 15, 2012, at 2:54 PM, dag at cray.com wrote: >> >>> Looking through TOT sources, I don't see anything that would provide >>> def/use chains (or equivalent information) post register allocation. I >>> would like to

Hi folks, I would like to find out the machine instructions that use some given registers in the reverse order, and I came across these iterators (use_iterator/reg_iterator). However, there are two things I noticed: 1) These iterators seem to traverse the machine function a bit differently from what I get from the machine function dump. In other words, the use_iterator list is not constructed in

Patch for review. On Mon, Aug 21, 2017 at 11:45 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> wrote: > Ping. > > Still working on preparing code for review. Will have a patch for review > ready in the coming days. > > PL > > On Tue, Aug 15, 2017 at 12:06 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> > wrote: > >> Hi, >> >> >>

Thanks Quentin. I'm trying to examine from the operands of the return instruction, and then to get the last assignment of those. I thought use_iterator/reg_iterator may suit better than just loop through the machine basicblock in the reverse order. Cheng-Chih On Thu, Sep 25, 2014 at 1:51 PM, Quentin Colombet <qcolombet at apple.com> wrote: > Hi Cheng-Chih, > > On Sep 25,

I tried debugging it and the issue seems to be in the implementation of MachineInstrIterator.h and the way it interacts with GraphWriter.h functions. I found this by replacing the ( template <> struct GraphTraits<MCDFGraph<MachineFunction*> >) with a similar MCDFGraph based template of CFG similar to the one in MachineFunction.h (similarly replacing the DOTGraphTraits with the

In LiveIntervals::processImplicitDefs() we have this: for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg), UE = mri_->use_end(); UI != UE; ) { MachineOperand &RMO = UI.getOperand(); MachineInstr *RMI = &*UI; ++UI; MachineBasicBlock *RMBB = RMI->getParent(); if (RMBB == MBB) continue; const

Andy, I traced my problem to this point: In ScheduleDAGInstrs.cpp we have the following function: /// addVRegDefDeps - Add register output and data dependencies from this SUnit /// to instructions that occur later in the same scheduling region if they read /// from or write to the virtual register defined at OperIdx. /// /// TODO: Hoist loop induction variable increments. This has to be ///

On Jun 13, 2012, at 10:49 AM, Sergei Larin <slarin at codeaurora.org> wrote: > So if this early exit is taken: > > // SSA defs do not have output/anti dependencies. > // The current operand is a def, so we have at least one. > if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) > return; > > we do not ever get to this point: > >

Andy, Thanks for reply. I was able to trace the problem to the MI DAG dep constructor. See this: SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10 # preds left : 0 # succs left : 0 # rdefs left : 1 Latency : 1 Depth : 0 Height : 0 SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0;

Hi, I am trying to generate the DFG of machine functions. Initially, I added a pass to generate the DFG of LLVM IR functions. This was based on the mail thread - http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-September/025582.html. This pass worked fine and I was able to generate DFG of LLVM IR functions. Later, I ported the DFG pass code for machine functions. I ported the InstIterator.h

Hi all, How can I get a reference to an instruction if I have a reference to an operand? For example, let suppose I have a reference to the ConstantExpr "getelementptr inbounds" in the following instruction: %4 = getelementptr i32* getelementptr inbounds ([8 x i32]* @__mem_grid_MOD_nnyp, i32 0, i32 0), i32 %3 then, how can I get a reference to the GetElementPtrInst object? The

On Jul 17, 2009, at 7:57 AM, David Greene wrote: > In LiveIntervals::processImplicitDefs() we have this: > > for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg), > UE = mri_->use_end(); UI != UE; ) { > MachineOperand &RMO = UI.getOperand(); > MachineInstr *RMI = &*UI; > ++UI; > MachineBasicBlock *RMBB

Eduardo <erocha.ssa at gmail.com> writes: > How can I get a reference to an instruction if I have a reference to > an operand? For example, let suppose I have a reference to the > ConstantExpr "getelementptr inbounds" in the following instruction: > > %4 = getelementptr i32* getelementptr inbounds ([8 x i32]* > @__mem_grid_MOD_nnyp, i32 0, i32 0), i32 %3 >

In the following IR module: – define i8 @foo() #0 { entry: %call0 = call i8 @bar() ret i8 %call0 } declare i8 @bar() #1 – @bar() gets marked as its own user in top-of-tree LLVM. I patched the Verifier to check it (but didn’t commit the patch): – Index: lib/IR/Verifier.cpp =================================================================== --- lib/IR/Verifier.cpp (revision 203468) +++

Hello all, I am a LLVM newer who want to obtain the use-def chain for all instruction of a sample code, for this purpose i use the following code. ///////////////sample code:///////////////////////// #include <stdlib.h> #include <stdio.h> #include <time.h> #define ARRAY_SIZE 5 int main() { int x, y, holder; int k,z,f,i; z=0; f=0; k=0; for(x = 0; x < ARRAY_SIZE;

Hello everyone ! In my LLVM pass, there is `Intruction* I1`. All the used "I1"s are ICMP instructions. *I1->getOperand(0) returns a `Value*` type. From errs()<<"\n"<<*I1->getOperand(0)<<"\n"; //printed : %3 = load i32* %c, align 4 Printed as expected. But I want to use %c. Do you know how I can get %c ? I need to use the value %c in

Say I want to find all LLVM Value*-es that a live on exit from a basic block. What's the best way? - The 'LiveRange', 'LiveVariables' and 'LiveIntervals' classes seem to be tied to register allocation. - The ./lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.h file seem to provide what I need, but it's no a public header. - Volodya

On Friday 26 February 2010 19:09:01 Dan Gohman wrote: > I've now looked at your latest patch. In summary, it does expose a > subtle problem. I haven't seen anything that here would lead to > observable misbehavior yet though. Well, I'm definitely observing misbehavior. I know it has something to do with local changes here but I haven't isolated it yet. >